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High pressure metal oxide semiconductor element and its manufacturing method

A technology of oxide semiconductor and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as limited capacity, and achieve the effect of improving breakdown voltage

Active Publication Date: 2007-05-02
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Traditional DMOS components, whether LDMOS or VDMOS, have limited ability to increase the breakdown voltage

Method used

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  • High pressure metal oxide semiconductor element and its manufacturing method
  • High pressure metal oxide semiconductor element and its manufacturing method
  • High pressure metal oxide semiconductor element and its manufacturing method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0055] 3A to 3D are cross-sectional views showing the manufacturing process of the metal-oxide-semiconductor transistor device according to an embodiment of the present invention.

[0056] Referring to FIG. 3A , firstly, a substrate 300 is provided. The substrate 300 is, for example, an N-type silicon substrate.

[0057] Next, a buried N-type doped region 302 is formed in the substrate 300 . The buried N-type doped region 302 is formed by, for example, performing an ion implantation process using phosphorus as a dopant.

[0058] Then, an N-type epitaxial layer 304 is formed on the substrate. The method for forming the N-type epitaxial layer 304 is, for example, using phosphorus as a dopant to perform a chemical vapor deposition process in an in-situ doping method to form a layer of amorphous silicon material (not shown), and then the amorphous silicon material layer formed by a solid phase epitaxy step.

[0059] Next, please refer to FIG. 3B , an N-type well region 306 is ...

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Abstract

A semiconductor element of high pressure metal oxide is prepared as setting the first N type of well region under isolation structure and in N type of epitaxial layer at grid side, superposing the first N type of well region with N type of drain electrode region partially, setting buried N type of doped region in substrate under N type of epitaxial layer, electric-connecting buried N type of doped region to the first N type of well region and also arranging P type of well region and grating dielectric layer as well as N type of source electrode region on said semiconductor element.

Description

technical field [0001] The invention relates to a semiconductor element, in particular to a high-voltage metal oxide semiconductor element. Background technique [0002] When the size of metal-oxide-semiconductor devices shrinks, the shortened channel length will make the operation speed of the transistor faster, but the problems derived from the shortened channel will become more and more serious, that is, the so-called short channel Road effect (short channel effect). If the applied voltage remains the same and the channel length of the transistor is shortened, according to the formula of electric field = voltage / length, the energy of electrons in the channel will be accelerated by the electric field to increase, thereby increasing the electrical breakdown (electrical breakdown) On the contrary, the increase of the intensity of the electric field will also increase the energy of the electrons in the channel, and the phenomenon of electrical breakdown will also occur. [...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336
Inventor 李治华陈铭逸
Owner UNITED MICROELECTRONICS CORP
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