Method and apparatus for two-step polishing

Abstract

Methods and apparatus for planarizing a substrate surface having copper containing materials thereon is provided. In one aspect, the invention provides a method for polishing a substrate including polishing the substrate with an abrasive-free polishing pad until it is substantially planarized and then polishing the substrate with a fixed abrasive polishing pad to remove residual materials disposed thereon. Another aspect of the invention provides a computer readable medium bearing instructions for performing the method described herein. In another aspect, the invention provides a system for processing substrates including a first platen, an abrasive-free polishing pad disposed on the first platen, a second platen, a fixed abrasive polishing pad disposed on the second platen, and a computer based controller configured to cause the system to polish the substrate with an abrasive-free polishing pad; and then to polish the substrate with a fixed abrasive polishing pad to remove residual materials disposed thereon.

Description

[0001] 1. Field of the Invention[0002] The present invention relates generally to the fabrication of semiconductor devices and to chemical mechanical polishing and planarization of semiconductor devices.[0003] 2. Description of the Related Art[0004] Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of indi...

AI Technical Summary

Problems solved by technology

However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities.

Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.

One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern.

Etching with copper using traditional deposition / etch processes for forming interconnects has been less than satisfactory.

One challenge which is presented in copper polishing is that the interface between copper and the barrier layer is generally non-planar.

These challenges in copper removal often results in the retention of copper containing material, or residue, on the surface of the substrate.

Overpolishing of copper and the interface can result in forming topographical defects, such as concavities or depressions, referred to as dishing, and can further lead to non-uniform removal of the barrier layer disposed thereunder.

However, this two step "slurry-slurry" technique can still result in an unacceptable amount of dishing.

Dishing results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation.

Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.

However, fixed abrasive pads require frequent replacing due to wear and processes using fixed abrasive pads require longer polishing times which can result in lower substrate through-put.

However, an increased contact pressure during polishing has been observed to result in scratching and other defect formation on the surface of the substrate.

Scratching of the substrate surface can detrimentally affect subsequent processing of the substrate and detrimentally affect device fabrication and performance.

However, abrasive-free polishing techniques have exhibited difficulty in removing all of the copper material from the surface of the substrate which may remain as undesirable metal residues after the polishing process.

The presence of residual material can detrimentally effect subsequent polishing processes, such as barrier layer removal, and detrimentally affect the polish quality of the substrate surface.

Finally, the ability to planarize using an abrasive-free process or a process utilizing a very low concentration of abrasives results in lower production and operation costs.

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