Polishing composition for semiconductor wafers
a technology of semiconductor wafers and compositions, applied in lapping machines, manufacturing tools, other chemical processes, etc., can solve the problems of dimensional loss in circuit interconnections, excessive removal of unwanted metals from circuits, and affecting the continued fabrication of dual damascene structures
Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Applications(United States)
- Current Assignee / Owner
- Publication Date
- 2005-03-17
- Estimated Expiration
- Not applicable · inactive patent
Abstract
Description
BACKGROUND OF THE INVENTION
[0001] This invention relates to polishing of semiconductor wafers and, more particularly, to compositions and methods for removing wafer layers, such as, barrier materials, capping materials, dielectric layers, anti-reflective layers and hard masks in the presence of an underlying silicon carbide nitride layer.
[0002] Typically, semiconductor substrates have a silicon base and dielectric layers containing multiple trenches arranged to form a pattern of circuit interconnects within the dielectric layer. These trench patterns have either a damascene structure or dual damascene structure. In addition, typically one to as many as three or more capping layers coat the trench patterned dielectric layer with a barrier layer covering the capping layer or capping layers. Finally, a metal layer covers the barrier layer and fills the patterned trenches. The metal layer forms circuit interconnects that connect dielectric regions and form an integrated circuit. [0003...
Examples
example 1
[0034] In this test, the removal rates with addition of several alkanoamides are compared with control Slurry A. This test used a Strausbaugh polishing machine with an IC1010 polishing pad (Rodel, Inc.) under downforce conditions of about 2 psi (13.8 kPa) and a polishing slurry flow rate of 200 cc / min, a platen speed of 120 RPM and a carrier speed of 114 RPM polishing the sample wafers (200 mm). The polishing slurry had a pH of 9 adjusted with KOH or HNO3 and all slurries were made with a balance of deionized water.
[0035] The following table indicates that alkanoamide surfactants have the ability to suppress SiCN wafer removal rate while leaving the barrier and capping layer removal rates, including SiN, almost unaffected.
TABLE 1ConcentrationTaNTEOSCDOSiNTaSiCNCuΔ SiCN −Ratio ofSlurryAdditive(wt %)RRRRRRRRRRRRRRΔ SiNSiN / SiCNANone1564855242848066213046300.371Cocamide DEA0.1314667321393996208710811364.582Lauramide DEA0.1314767411164016187610711495.263Linoleamide DEA0.13147673511443...
example 2
[0037] In this test, the removal rates with addition of several polyethylene oxide type surfactants were compared with a control using the conditions of Example 2.
[0038] The following Table indicates that the polyethylene oxide surfactants used also have the ability to effectively suppress only SiCN wafer removal rate while leaving barrier and capping layer removal rates almost unaffected.
TABLE 2Concen-Ratio ofRatio oftrationTaNTEOSCDOSiCNCuSiNTaSiN / TaN / Δ SiCN −SlurryAdditive(wt %)RRRRRRRRRRRRRRSiCNCDOΔ SiNHLBBNone166572121751213784876680.400.80 6C18(EO)20OH0.03%168346226117303265822.8064.293615.3 7C12(EO)4OH0.03%150776411012794315393.4113.710319.1 8C16(EO)10OH0.03%16815152210803536163.2778.097112.9 9C18(EO)10OH0.03%15576292864523555265.5455.2101712.410C18(EO)10OH0.10%14564642747332654965.6054.194412.411C8(C6H4(EO)10OH0.10%164052842125843406102.7238.794110.412C8(C6H4(EO)35OH0.10%16725473273943596974.8852.3101117.9
RR = removal rate expressed in angstroms per minute.
Δ SiCN −Δ SiN ...