Polishing composition for semiconductor wafers

Abstract

An aqueous composition is useful for polishing semiconductor wafers. The composition comprises a nonionic surfactant that suppresses removal rate of silicon carbide-nitride and has a hydrophilic group and a hydrophobic group. The hydrophobic group has a carbon chain length of greater than three. And the nonionic surfactant suppresses silicon carbide-nitride removal rate at least 100 angstroms per minute greater than its decrease in silicon nitride removal rate as measured with a microporous polyurethane polishing pad pressure measured normal to a wafer of 13.8 kPa.

Description

BACKGROUND OF THE INVENTION

[0001] This invention relates to polishing of semiconductor wafers and, more particularly, to compositions and methods for removing wafer layers, such as, barrier materials, capping materials, dielectric layers, anti-reflective layers and hard masks in the presence of an underlying silicon carbide nitride layer.

[0002] Typically, semiconductor substrates have a silicon base and dielectric layers containing multiple trenches arranged to form a pattern of circuit interconnects within the dielectric layer. These trench patterns have either a damascene structure or dual damascene structure. In addition, typically one to as many as three or more capping layers coat the trench patterned dielectric layer with a barrier layer covering the capping layer or capping layers. Finally, a metal layer covers the barrier layer and fills the patterned trenches. The metal layer forms circuit interconnects that connect dielectric regions and form an integrated circuit. [0003...