Multi-chip module with third dimension interconnect

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Description

1. RELATED APPLICATIONS [0001] This application is a Continuation of U.S. patent application U.S. 2002 / 0138637 A1 filed on Mar. 22, 2001 titled “Computer Architecture and Software Cells for Broadband Networks,” and has at least one of the same inventors as the above referenced U.S. patent application.BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates in general to a multi-chip module with third dimension interconnect. More particularly, the present invention relates to one or more processor modules that includes one or more first buses in a first dimension and a memory module that couples to the processor modules using a third dimension interconnect and also includes one or more second buses in a second dimension. [0004] 2. Description of the Related Art [0005] The present invention relates to an architecture for computer processors and computer networks and, in particular, to an architecture for computer processors and computer networks in a ...

AI Technical Summary

Benefits of technology

The present invention provides a new architecture for computers, computing devices, and computer networks that allows for efficient and high-speed processing of applications and data. The architecture is based on a common computing module with a consistent structure and a shared dynamic random access memory (DRAM) with multiple sections and bank controllers. The invention also provides a synchronized system for accessing the shared DRAM, sandboxes for security, and a system for processing streaming data. Additionally, the invention provides an absolute timer for processing tasks and an alternative scheme for processing older applications. Overall, the invention improves the speed and flexibility of processing on computer networks.

Problems solved by technology

This heterogeneous combination of computers and computing devices on today's computer networks complicates the processing and sharing of data and applications.

The sharing of data and applications among this assortment of computers and computing devices presents substantial problems.

These techniques include, among others, sophisticated interfaces and complicated programming techniques.

These solutions often require substantial increases in processing power to implement.

They also often result in a substantial increase in the time required to process applications and to transmit data over networks.

While this approach minimizes the amount of bandwidth needed, it also often causes frustration among users.

This additional layer of software significantly degrades a processor's processing speed.

These viruses and malfunctions can corrupt a client's database and cause other damage.

Although a security protocol employed in the Java model attempts to overcome this problem by implementing a software “sandbox,” i.e., a space in the client's memory beyond which the Java applet cannot write data, this software-driven security model is often insecure in its implementation and requires even more processing.

These network applications require extremely fast processing speeds.

The current architecture of networks, and particularly that of the Internet, and the programming model presently embodied in, e.g., the Java model, make reaching such processing speeds extremely difficult.

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