Semiconductor integrated circuit device

Abstract

To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a semiconductor integrated circuit device, particularly to a semiconductor integrated circuit device preferable for carrying out defect redundancy of a memory cell array without increasing fabrication cost in a highly-integrated semiconductor integrated circuit using multiple layer wirings. BACKGROUND OF THE INVENTION [0002] Conventionally, in defect redundancy in multiple layer wirings, as a system of programming a location where the defect is disposed, there has been used a method of cutting polysilicon by laser beam or a method of cutting wirings by laser beam. The method is as described in an example executed in DRAM of IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 418-419. [0003] When introducing defect redundancy to a semiconductor integrated circuit, in order to reduce cost, the following elements must be considered. [0004] (1) Preventing fabrication steps from increasing. [00...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor integrated circuit device with a memory cell array and redundant memory cells for replacing defective cells. The device also includes a nonvolatile memory for storing redundant address information and a redundant decoder for controlling to switch a connection between an output from the memory cell array and an output from the redundant memory cells. The nonvolatile memory includes a first semiconductor area and a second semiconductor area and a floating gate arranged to interpose an insulating film between the first and the second semiconductor areas and the floating gate. The device also includes a redundant data writing process for the nonvolatile memory during testing of the semiconductor integrated circuit. The technical effect of the invention is to provide a reliable and efficient solution for replacing defective memory cells in a semiconductor integrated circuit device.

Problems solved by technology

Further, redundant data is written to the nonvolatile memory in testing the semiconductor integrated circuit mounted therewith.

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