New fuse structure

Abstract

An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 60 / 583,637, filed on Jun. 29, 2004, entitled “E-Fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit,” which application is hereby incorporated herein by reference.TECHNICAL FIELD [0002] This invention relates generally to an electrical fuse and more particularly to an electrical fuse having a vertical structure. BACKGROUND [0003] In the semiconductor industry, fuse elements are widely used features in integrated circuits for a variety of purposes, such as improving manufacturing yield or customizing a generic integrated circuit. For example, by replacing defective circuits on a chip with redundant circuits on the same chip, manufacturing yields can be significantly increased. Replacing defective circuits is especially useful for improving manufacturing yield of the memory chips since memory chips consist of a lot of identical memory cells and cell groups. By selectively...

AI Technical Summary

Benefits of technology

[0012] The vertical structure of the preferred embodiment is suitable to be formed in any layer and saves layout space. The embodiments of the present invention have several advantageous features. Firstly, higher repairable rates can be achieved since the burn out process is easier to control and more reliable. Secondly, fewer masking layers are required, therefore reducing costs. Thirdly, the fuse may reside in any region of the inter layer vias for cell size reduction. This provides a flexible structure for circuit design.

Problems solved by technology

However, the laser repair rate in various structures such as in lower level metal layers is low and the process is complex. FIG. 1 illustrates a laser fuse formed close to the surface of a chip.

If a laser fuse 10 is in a lower level layer deep in a chip, as shown in FIG. 2, the opening 8 will be deeper, while the thickness T of the oxide still has to be controlled precisely, which increases the complexity significantly and decreases the repairable rate.

This decreases the device reliability and increases the production cost.

However, the repairable rate is still not satisfactory.

There are several disadvantages faced by conventional methods of making fuses.

Firstly, the repairable rate is typically low.

Secondly, the additional masking layer needed for laser repair incurs higher costs.

The process is also more complex with higher uncertainty.

Thirdly, the structure design is not flexible.

Fuses typically have to be designed in higher layers, as it is harder to form deep laser trenches through to lower layers.

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