Interconnect line selectively isolated from an underlying contact plug

a contact plug and interconnect line technology, applied in the field of semiconductor devices, can solve the problems of increasing the potential for shorting between adjacent electrical conductors, the close proximity of discrete electrical features within memory cells, and the problem of integrating circuit designers facing problems related to each other, so as to achieve efficient connection of interconnect lines and higher integration levels
US20060033123A1Inactive Publication Date: 2006-02-16DRYNAN JOHN M
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
DRYNAN JOHN M
Publication Date
2006-02-16
Estimated Expiration
Not applicable · inactive patent

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Abstract

The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.
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Description

[0001] This application is a divisional of U.S. patent application Ser. No. 10 / 863,203, filed Jun. 9, 2004, which is a divisional of U.S. patent application Ser. No. 10 / 214,169, now U.S. Pat. No. 6,781,182, filed Aug. 8, 2002, which is a divisional of U.S. patent application Ser. No. 09 / 595,922, now U.S. Pat. No. 6,511,879, filed Jun. 16, 2000. The entirety of each of these applications and patents is hereby incorporated by reference herein.BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a semiconductor device and a method of manufacturing such a device, wherein signal lines (e.g., bit lines of a memory device, etc.) may be isolated from adjacent electrical conductors.

[0004] 2. Discussion of the Related Art

[0005] Modern integrated circuit designers confront problems related to the need for increasingly smaller size and higher levels of integration. In the art of integrated circuit fabrication, and particularly when dealing with modern ...

Claims

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