Structure and method for enhanced triple well latchup robustness

Abstract

Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Description

BACKGROUND [0001] 1. Field of the Invention [0002] The embodiments of the invention generally relate to metal oxide semiconductor field effect transistor (MOSFET) devices, and, more particularly, to triple well technology in such MOSFET devices. [0003] 2. Description of the Related Art [0004] Both noise isolation and the elimination of CMOS latchup are significant issues in advanced complementary metal oxide semiconductor (CMOS) technology and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology. More particularly, as MOSFET threshold voltages decrease, the need to isolate circuitry from noise sources becomes more important and has lead to an increased interest in “isolated MOSFETs” (i.e., triple well technology). In current triple well technology, a buried n-type layer (i.e., a buried n+ layer) is placed below the p-well and a buried p-type layer (i.e., a p+ layer) is placed below the n-well (or n-well / sub-collector combinations) at the same level, but not displaced. The burie...

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Benefits of technology

[0015] To further improve latchup robustness within the device, the method can comprise before forming the first semiconductor well, forming a sub-collector region with the second conductivity type above one side of the second semiconductor layer and then, forming the first semiconductor well above the sub-collector region.

Problems solved by technology

Both noise isolation and the elimination of CMOS latchup are significant issues in advanced complementary metal oxide semiconductor (CMOS) technology and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology.

Additionally, because the buried n+ layer must overlap the n-wells in order to isolate the p-well, spacing issues present a problem in the current triple well CMOS formation process.

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