Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions

Abstract

A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Description

TECHNICAL FIELD [0001] The present invention is related to the use of shallow trench isolation (STI) in the design and fabrication of integrated circuits, and, more specifically, avoiding damage to the field oxide in STI regions during subsequent processing steps in the fabrication of an integrated circuit device. BACKGROUND INFORMATION [0002] In the design and fabrication of integrated circuits, it is necessary to isolate adjacent active devices from one another so that leakage currents between devices do not cause the integrated circuits to fail or malfunction. As dimensions of semiconductor devices have shrunk, shallow trench isolation (STI) techniques have largely replaced other isolation techniques such as LOCOS. In fabricating an STI region, conventional photolithography and etching techniques may be used to create trenches in the integrated circuit substrate. The trenches may then be filled with one or more insulating materials, such as thermal silicon oxide. The wafer may th...

AI Technical Summary

Benefits of technology

This method effectively avoids damage to the polysilicon layer and field oxide in STI regions, maintaining the integrity of the isolation properties and surface smoothness, thus preventing gap-fill issues in subsequent processing steps.

Problems solved by technology

The reflections may have detrimental effects on the quality and accuracy of the resulting mask.

A conventional wet strip process may use hot phosphoric acid which may damage the polysilicon layer underlying the ARC layer; whereas, a conventional plasma etching process may cause extensive gouging in any exposed field oxide, including in the thermal oxide in an STI region.

Further, gouges in STI regions may create an uneven surface causing gap-fill problems for subsequent processing of the device wafer.

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