Nonvolatitle memory array and method for operating thereof

Abstract

A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 95121186, filed on Jun. 14, 2006. All disclosure of the Taiwan application is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of Invention[0003]The present invention relates to a nonvolatile memory array and method for operating the same. More particularly, the present invention relates to a mixed nonvolatile memory array and method for operating the same.[0004]2. Description of Related Art[0005]Among the various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used inside personal computer systems and electron equipment. Data can be stored, read out or erased from the EEPROM many times and stored data are retained even after power supplying the devices is cut off.[0006]Typically, the floating gates and the control gates of the EEPROM non-volatile...

AI Technical Summary

Benefits of technology

[0010]Accordingly, at least one objective of the present invention is to provide a nonvolatile memory cell. In the present invention, the nitride layer in the oxide / nitride / oxide layer is used as a carrier trapping element. Furthermore, a doped region with a relatively small thickness is used as a source / drain region and the channel region under the gate structure. Hence, by applying a voltage on the gate structure and a bias on the terminals of the doped regions, the channel under the gate structure can be well controlled to perform the operations such as programming, reading and erasing process. In addition, every two-feature-size square region possesses at least two carrier storage spaces.

[0016]In the present invention, since the silicon nitride layer of the silicon oxide / silicon nitride / silicon oxide layer is served as a carrier trapping element and the doped region with a relatively small thickness is used as source / drain region and the channel region between the source / drain regions can be controlled by applying voltages on the gate structure and the source / drain region so as to operate the nonvolatile memory cell, the manufacturing method is relatively simple and the cost is decreased as well.

[0020]For each memory cell of the present invention, there are a depletion mode memory cell and an enhanced mode memory cell. Hence, the density of the carrier storage space is increased. That is, for each 4F2 region, there are at least four carrier storage spaces. By comparing with the conventional nitride read-only memory, the mixed nonvolatile memory array of the present invention does not need a buried diffusion oxide layer structure, and the oxide / nitride / oxide layer under the gate is completely remained.

[0027]Since the oxide / nitride / oxide layer is used as a carrier trapping element and the doped region with a relatively small thickness is used as source / drain region and the channel region between the source / drain regions, the manufacturing method is relatively simple and the cost is decreased as well. Furthermore, there are at least four carrier storage spaces in a two-feature size square region so that the carrier storage density is increased. By comparing with the conventional nitride read-only memory, the mixed nonvolatile memory array of the present invention does not need a buried diffusion oxide layer structure, and the oxide / nitride / oxide layer under the gate is completely remained.

Problems solved by technology

However, if the tunneling oxide layer underneath the polysilicon gate contains some defects, a leakage current may develop leading to possible reliability problems in the device.

Hence, the production cost is increased beside the addition of one more ion implantation process.

Furthermore, in a two-time-feature-size square region, the unit memory device only provides two carrier storage space.

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