Method and Apparatus for Measuring Device Mismatches

Abstract

A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row / column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to the design and testing of integrated circuits, and more particularly to a method and system for testing an array of electronic devices formed on an integrated circuit.[0003]2. Description of the Related Art[0004]Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, c...

AI Technical Summary

Benefits of technology

[0012]It is therefore one object of the present invention to provide an improved method of testing an array of electronic devices which provides high spatial resolution of measurements, e.g., capable of measuring current mismatches between two minimal strength devices in close proximity.

[0013]It is another object of the present invention to provide such a method which may be implemented in an array having a large number of devices under test while reducing or minimizing resource cost.

Problems solved by technology

An IC may include a very large number of cells and require complicated connections between the cells.

Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers.

While the outputs of circuit 10 provide a fair basis to characterize the response of the devices, the measurements are not completely accurate since they fail to take into consideration various effects on signal creation and transmission.

Calibration of the measurement circuitry does not compensate for variations in the loading effects.

Moreover, spatial variability in integrated circuits is becoming worse due to variations such as Leff variation, doping concentrations, spurious leakage, systematic variation due to chemical mechanical planarization, etc.

Existing test structures cannot adequately account for the variability in these measurements.

In order to reliably characterize the variabilities, hundreds of samples are needed, which is even more impractical given the limited number of input / output (C4) pads provided on the circuits.

Circuit designers make assumptions about spatial variations of parameters which have a significant impact on product performance, but there is no reliable system for verifying these assumptions.

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