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Autonomic SMT System Tuning

a technology of automatic system tuning and smt, applied in the direction of genetic algorithms, instruments, digital computers, etc., can solve the problems of two copies often interfering with each other, processing often using a speed-increasing speed, and difficult multitasking for general tasks, so as to minimize latency, optimize processing workload, and increase throughput

Inactive Publication Date: 2008-07-24
MOILANEN JACOB LORIEN +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The invention provides methods, systems, and media for autonomic system tuning of SMT (Simultaneous Threading) for optimized processing of workloads on computer systems. The method involves calling an SMT scheduler with a hook into a genetic library to obtain genetic data from a genetic library for the optimized processing of the workload. The genetic data can be used to tune the SMT settings for a computer system to increase throughput, minimize latency, minimize power consumption, or achieve other performance metrics. The system includes a kernel, an SMT scheduler with a hook into a genetic library, a genetic data module of the genetic library with genetic data necessary for the optimized processing of the workload, and a control module of the genetic library for providing the genetic data to the SMT scheduler. The invention also provides a machine-accessible medium containing instructions for autonomic tuning of SMT settings for optimized processing of a workload on a computer system."

Problems solved by technology

Multitasking for general tasks is often fairly difficult because various programs holding internal data, known as state.
However, if another copy of the program is running on another processor, the two copies can interfere with each other by both attempting to read and write their state at the same time.
Another problem is that processors often use a speed-increasing technique known as caching in which small pools of very fast memory are associated with each processor in order to allow them to work with temporary values very quickly.
This can lead to a situation in which each processor is working in a separate cache, rather than in the shared memory; changes to a processor's local cache will not be communicated to other processors until the contents of the cache are written to shared memory.
This cannot be helped via programming techniques because it is invisible to the programs themselves.
Operating system functions are typically mapped into each virtual address space and interrupt handling typically runs in whichever memory context is in place when the interrupt occurs, so programs are still vulnerable to malfunctioning system code.
This can create problems if a thread is waiting for a resource to become available.
The disadvantage to preemptive multithreading is that the system may make a context switch at an inappropriate time, causing priority inversion or other bad effects which may be avoided by cooperative multi threading.
Despite advantages often obtained in processor performance through SMT, problems remain.
Recent state of the art reports indicate that always enabling SMT is not always beneficial.
In fact, performance of some applications with SMT enabled results in detrimental effects; performance is known to drop by as much as half.

Method used

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Examples

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Embodiment Construction

[0021]The following is a detailed description of example embodiments of the invention, a description further enhanced by the accompanying drawings. The embodiments are examples and are in such detail as to clearly communicate the invention. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The detailed descriptions below are designed to make such embodiments obvious to a person of ordinary skill in the art.

[0022]Generally speaking, systems, methods, and media for autonomic system tuning of simultaneous multithreading (“SMT”) are contemplated. Before discussing details of the invention, however, a discussion of the problem and invention's purpose ensues. After this preliminary discussion, details of the invention follow.

[0023]Many modern centra...

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Abstract

Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.

Description

CROSS REFERENCE[0001]This application is a continuation application of U.S. patent application Ser. No. 10 / 965,152 entitled AUTONOMIC SMT SYSTEM TUNING, attorney docket number AUS920030885US1 (4066), filed Oct. 14, 2004, the disclosure of which is incorporated herein in its entirety for all purposes.FIELD OF INVENTION[0002]The invention generally relates to autonomic system tuning of simultaneous multi-threading (“SMT”). More particularly, the invention relates to methods, systems, and media for autonomic system tuning of SMT by employing a genetic algorithm to determine whether to turn SMT on or off depending on the particular workload, whereby turning on SMT only enhances processor performance.BACKGROUND[0003]Many programming languages, operating systems, and other software development environments support “threads of execution,” or, as more commonly called, “threads.” Threads are similar to processes, which are tasks that take turns running on the central processing unit (cpu) of...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06N3/12G06F15/18
CPCG06N3/126
Inventor MOILANEN, JACOB LORIENSCHOPP, JOEL HOWARD
Owner MOILANEN JACOB LORIEN
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