Circuit and method for a three dimensional non-volatile memory

Abstract

An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Description

TECHNICAL FIELD[0001]The present invention relates to a circuit and method for providing a three dimensional non-volatile memory cell using charge trapping storage in a silicon oxide nitride-oxide ONO silicon (SONOS) flash memory device. The cell incorporates a uniform doping for the source, drain and channel regions. In one preferred embodiment a FinFET form is used another preferred embodiment a fully-depleted silicon on insulator (FD-SOI) form is used. The cell utilizes a charge trapping transistor using ONO or other similar dielectrics. A plurality of these non-volatile memory cells may be arranged in three dimensions using vertical layers. Processing methods are presented for fabricating integrated circuits incorporating memory portions using the SONOS cells. These cells are particularly useful to increase the density of a Flash NAND memory array because the uniform doping in the source, drain and channel circumvents thermal source and drain out diffusion problems that occurred...

AI Technical Summary

Benefits of technology

The present invention provides improved circuits and methods for manufacturing an improved SONOS non-volatile storage cell, three dimensional circuit arrays, and semiconductor processes for use in an integrated circuit. The invention solves thermal diffusion problems associated with repeated thermal cycles used to form three dimensional arrays of SONOS storage cells. The invention also provides three dimensional memory arrays that are highly integrated and provide a compact non-volatile memory array. The invention also provides discrete memory integrated circuits using the three dimensional arrays of SONOS cells. The methods of manufacturing the cells involve forming regions of source, drain, and channel material in a first direction, and uniformly doping them. ONO dielectric layers are formed over the polysilicon regions, and polysilicon gate regions are formed overlying the ONO dielectric. The invention allows for the formation of multiple layers of cells without requiring additional planar area on the integrated circuit. The technical effects of the invention include improved performance and reliability of the SONOS non-volatile storage cell, as well as more efficient and compact memory arrays.

Problems solved by technology

In FIG. 1, the undesired additional thermal diffusion of the source and drain regions is shown, if this undesired diffusion continues over many process steps the two regions may even electrically contact and close the channel region between them, causing device failure.

Even if such a failure does not occur, the source and drain diffusion changes the channel length, and affects the operation of the device after it is completed, resulting in unpredictable threshold voltages (Vt) and other deleterious effects.

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