Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same

Abstract

A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to European Patent Application No. 07121292.2 filed Nov. 22, 2007 and U.S. Provisional Application Ser. No. 60 / 990,130 filed Nov. 26, 2007, the contents of which are incorporated by reference herein in its entirety.TECHNICAL FIELD OF THE INVENTION[0002]The present invention relates to a non-volatile memory device and a method for manufacturing a non-volatile memory device.BACKGROUND OF THE INVENTION[0003]Erase saturation refers to the inability to erase a floating gate memory cell by removing charge from the floating gate to the Si channel through the tunnel oxide. This effect occurs because the parasitic current injected from the control gate towards the floating gate through the interpoly dielectric. The same problem arises in charge trapping non-volatile memory cells in which charge is stored in a charge trapping gate and the upper dielectric is called the blocking dielectric.[0004]A way to avoid erase ...

AI Technical Summary

Benefits of technology

[0007]In one embodiment, the control gate, or at least a bottom layer thereof which is in contact with the second dielectric, is constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k (i.e. k>kSiO2) materials after full device fabrication. Furthermore, the second dielectric, or at least a top layer thereof which separates the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. As a result, a separation is achieved between the material of at least the bottom layer of the control gate and a high-k material of the group which may be present in the second dielectric below the top layer. Consequently, a reduction in the work-function of the material of at least the bottom layer of the control gate after full device fabrication can be avoided and it can more easily be provided that the work-function at the interface between control gate and second dielectric is high enough to avoid or at least reduce erase saturation.

[0008]In one embodiment, the top layer is constructed in the second dielectric in an additional step before applying the control gate. In the embodiment, the second dielectric or an upper part thereof is constructed in a high-k material of the specified group and the mentioned reduction in work-function is counteracted by nitridation of this high-k material before applying the control gate. This nitridation is preferably performed by means of a Decoupled Plasma Nitridation (DPN) step or an ammonia anneal step. The result of the nitridation is that the material properties of the high-k material at least at the interface with the control gate are altered, in such a way that a reduction in the work-function of the material of the control gate at the interface no longer occurs or is at least partially suppressed. The nitridation step has the effect that at least a top layer is created in the second dielectric which is in nitrided high-k material, i.e. no longer in the specified group of high-k materials. The layer thickness of the high-k material and the nitridation step may also be chosen such that substantially the whole layer of high-k material is nitrided or even the whole of the second dielectric is made up of the nitrided high-k material. An additional advantage of this nitridation step is that the trap density in the high-k layer can be decreased, which may improve the retention ability of the non-volatile memory device.

Problems solved by technology

The same problem arises in charge trapping non-volatile memory cells in which charge is stored in a charge trapping gate and the upper dielectric is called the blocking dielectric.

However, metal gates are difficult to integrate in a conventional process flow.

In addition, they show a tendency to change the effective workfunction towards midgap, when deposited on some dielectric materials, likely consequence of the inherent thermal steps following their deposition.

Use of a p-type poly-silicon control gate, as is a trend nowadays, may be compromised by this so-called Fermi level pinning (FLP) effect.

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