Reduction of sti corner defects during spe in semicondcutor device fabrication using dsb substrate and hot technology

Abstract

A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Description

[0001]This is a continuation of U.S. application Ser. No. 11 / 847,053 filed Aug. 29, 2007, the entirety of which is incorporated herein by reference.FIELD OF INVENTION[0002]The invention relates generally to semiconductor devices and more particularly to methods for reducing corner defects generated during SPE in shallow trench isolation in the manufacture of semiconductor devices.BACKGROUND[0003]Complementary metal oxide semiconductor (CMOS) devices (e.g., NMOS or PMOS transistors) have conventionally been fabricated on semiconductor workpieces with a single crystal orientation (e.g., silicon having a Miller index (100)). Transistors within the CMOS devices, for example, are used in cell phones, laptop computers, etc., requiring greater speed, lower power consumption, higher reliability, and the like. The speed of the devices can be improved by increasing electron mobility, hole mobility, or both, using hybrid orientation technology (HOT). Electron mobility / movement for NMOS devices...

AI Technical Summary

Benefits of technology

The invention provides a device and method for making a semiconductor device with reduced residual STI corner defects. This is achieved by forming a direct silicon bonded substrate where a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, and then patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench. The method also includes implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Problems solved by technology

The ever decreasing size and scale of semiconductor device technology has presented numerous challenges.

For example, gate leakage current due to sharp corner effects in thin silicon gate oxide is a more pronounced problem with smaller devices.

These sharp features can also increase stresses, produce large electric fields, create dislocations in the silicon, and ultimately fail the device, for example.

These defects can and have been corrected with extremely high temperature anneals (e.g., greater than 1250 degrees Celsius); however those temperatures can cause other defects, such as large stresses that can warp the workpiece, and the like.

Advantages of this approach include no lateral templating; however there are trench edge and corner defects created using this technology from vertical templating and the like.

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