Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems

Active Publication Date: 2012-07-05
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0010]Generally, and in one form of the invention, an electronic circuit includes a microcontroller processor, a peripheral coupled with the processor, an endian circuit coupled with the processor and the per

Problems solved by technology

An important problem in the art involves the challenge of ensuring that the intended electronic operations represented by such configuration bits are actually carried into effect.
Also, the risk of errors and reliability

Method used

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  • Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems
  • Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems
  • Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems

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Example

[0027]Corresponding numerals in different Figures indicate corresponding parts except where the context indicates otherwise. A minor variation in capitalization or punctuation for the same thing does not necessarily indicate a different thing. A suffix .i or .j refers to any of several numerically suffixed elements having the same prefix.

DETAILED DESCRIPTION OF EMBODIMENTS

[0028]In FIG. 1, a flash module 100 includes banks 110.i of flash memory that include at least some one-time programmable (OTP) memory space 115. The flash memory banks 110.i are coupled with a flash wrapper circuitry 120 that includes a flash bank interface coupled with the banks 110.i. A data path logic block is coupled with the flash bank interface. The data path logic block is also coupled with a Control and DFT (Design for Test) block, and together they are also called a flash memory controller FMC 130 herein.

[0029]The data path logic block communicates with a special BUS2 interface 140 (BUS2intf), a CPU bus i...

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Abstract

An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to Provisional U.S. Patent Application “Dual Endianess and Other Configuration Safety in Lock Step Dual-Core System, and Other Circuits, Processes and Systems” Ser. No. 61 / 565,024 (TI-70172 PS1) filed Aug. 18, 2011, for which priority is claimed under 35 U.S.C. 119 and all other applicable law, and which is incorporated herein by reference in its entirety.[0002]This application is related to Provisional U.S. Patent Application “Dual Endianess Safety in Lock Step Dual-Core System” Ser. No. 61 / 427,048 (TI-70172PS) filed Dec. 23, 2010, for which priority is claimed under 35 U.S.C. 119 and all other applicable law, and which is incorporated herein by reference in its entirety.[0003]This application is related to US Patent Application Publication 20110225475 (TI-66395) dated Sep. 15, 2011, “A Low Overhead and Timing Improved Architecture for Performing Error Checking and Correction for Memories and Buses in System-O...

Claims

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Application Information

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IPC IPC(8): G06F11/14
CPCG06F11/1048G06F11/1641G06F11/1654G11C29/52G11C29/00G06F11/1068H03M13/27G06F11/1016G06F11/1008G11C29/14G11C29/48G11C2029/0411H03M13/13G06F13/4013G06F9/3004G06F9/30076G06F11/28G06V10/955G06F11/0763
Inventor XIAO, YANYANGPALUS, ALEXANDRE PIERREGREB, KARL FRIEDRICHLAVERY, KEVIN PATRICKKRAUSE, PAUL
Owner TEXAS INSTR INC
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