Semiconductor memory device and method of manufacturing the same

Inactive Publication Date: 2015-08-06
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0030]Unnecessary voltage drop can be prevented in a MOS transistor where the threshold has risen due to the back gate effect. This eliminates the need for a device having a voltage higher than a

Problems solved by technology

This limitation on withstand voltage is an obstacle to a reduction in device size for the purpose of chip size shrinking, and lowering the voltage Vpp is therefore demanded.
However, if the voltage Vpp is simply lowered, electric charge injection to the floating gate, which is important as a memory function, cannot be accomplished fully.
The thinning of the tunnel oxide film 07 described above, however, impairs retention characteristics of the memory and accordingly lowers the reliability of the memory.
In addition to this hard-to-overcome trade-off relation, an unnecessary voltage drop in a MOS transistor that is connected in series in a location between the booster circuit and the memory main bo

Method used

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  • Semiconductor memory device and method of manufacturing the same
  • Semiconductor memory device and method of manufacturing the same
  • Semiconductor memory device and method of manufacturing the same

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Experimental program
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first embodiment

[0042]FIGS. 1A to 1C are diagrams illustrating an EEPROM according to a first embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is a sectional view taken along the line C-C′, and FIG. 1C is a perspective view.

[0043]The EEPROM of the present invention includes, similarly to the related-art EEPROM that is illustrated in FIGS. 8A to 8C, a memory main body portion 02 and a select gate transistor portion 01 for selecting the memory main body portion 02. The basic operation principle of the EEPROM of FIGS. 1A to 1C is the same as that of the related-art EEPROM described above, and the sectional view of FIG. 1B is also the same as FIG. 8B. The difference is that the select gate transistor portion 01 of the present invention is formed of a fin-shaped single-crystal semiconductor thin film that stands like a wall.

[0044]The select gate transistor portion 01 is formed of a fin-shaped single-crystal semiconductor thin film created by a process in which a p-type silicon substr...

second embodiment

[0049]A second embodiment of the present invention is described with reference to FIGS. 3A to 3C. The second embodiment is a modification of the EEPROM of FIGS. 1A to 1C according to the first embodiment, and is obtained by forming the memory main body portion 02 into a fin shape as well. FIG. 3A is a plan view, FIG. 3B is a sectional view taken along the line E-E′, and FIG. 3C is a perspective view. Sectional views of the structure of FIGS. 3A to 3C that are taken along the line C-C′, which runs from the drain n+ region 04 of FIGS. 1A to 1C toward the source n+ region 08, and the line D-D′, which runs along the width direction of the select gate, are the same as those in the first embodiment, and are therefore omitted.

[0050]As illustrated in FIG. 3A, the memory main body portion 02 in this embodiment is formed on surfaces of a fin-shaped single-crystal semiconductor thin film, which forms the p-type silicon substrate 05 thinned to have the same thickness as that of the select gate ...

third embodiment

[0052]A method of manufacturing the EEPROM of the first embodiment that has a fin shape only in the select gate is described next with reference to FIGS. 4A to 4D.

[0053]First, ion implantation or the like is used to form a plurality of n− regions 20 in parallel on the p-type semiconductor substrate 05 as illustrated in FIG. 4A. The notation “n−” indicates the relative level of the n-type impurity concentration, which satisfies a relation n−+. Thereafter, a plurality of trenches that can serve as shallow trench isolation (STI) regions are formed so as to be orthogonal to the n− regions 20. STI internal oxide films 17 are embedded in concave portions of the trenches. The step of forming the n regions and the step of forming the STI regions may be switched with each other in the order.

[0054]Next, as illustrated in FIG. 4B, the STI internal oxide films 17 are partially removed by etching to form a fin-shaped single-crystal semiconductor thin film. The select gate is formed along the reg...

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Abstract

Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

Description

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Claims

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Application Information

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Owner SII SEMICONDUCTOR CORP
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