Semiconductor memory device and method of manufacturing the same

Abstract

Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON / OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor memory device.[0003]2. Description of the Related Art[0004]A related-art semiconductor memory device is described taking an EEPROM as an example. FIGS. 8A to 8C are conceptual diagrams of a related-art EEPROM that has a general structure as described in Japanese Patent Application Laid-open No. 2004-71077. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line A-A′ of FIG. 8A, and FIG. 8C is a perspective view.[0005]The EEPROM includes a memory main body portion 02 and a select gate transistor portion 01 for selecting the memory main body portion 02. In the memory main body portion 02, an electrode called a floating gate 12, which accumulates electric charges, is formed. The state of the memory is changed depending on an amount of the electric charges. Here, accumulating electric charges in the floating gate 12 puts the memory main body portion 02 into a...

AI Technical Summary

Benefits of technology

The patent text is describing a way to prevent voltage drops in a specific type of transistor. By doing so, the device can perform its memory writing duties at a lower voltage, which reduces the need for extra voltage and keeps the device size down. Additionally, this method improves the transistor's ability to switch on and off, which is important for its overall performance.

Problems solved by technology

This limitation on withstand voltage is an obstacle to a reduction in device size for the purpose of chip size shrinking, and lowering the voltage Vpp is therefore demanded.

However, if the voltage Vpp is simply lowered, electric charge injection to the floating gate, which is important as a memory function, cannot be accomplished fully.

The thinning of the tunnel oxide film 07 described above, however, impairs retention characteristics of the memory and accordingly lowers the reliability of the memory.

In addition to this hard-to-overcome trade-off relation, an unnecessary voltage drop in a MOS transistor that is connected in series in a location between the booster circuit and the memory main body portion 02 presents further obstacle to the fulfillment of the request to lower the device withstand voltage.

However, because this voltage is calculated as Vpp+Vth′=15+2=17 V, securing a withstand voltage of 17 V is still necessary and an excess withstand voltage still needs to be secured, which causes difficulty in reducing device size.

Increasing Cox is accomplished by thinning the gate oxide film 03, but there is a limit to the thinning because of the withstand voltage.

Lowering the impurity concentration also has a limit because of its effect on leakage of the MOS transistor.

Thus, shrinking the chip size by lowering the device withstand voltage is very difficult due to various limitations.

Images