Memory structure and manufacturing method thereof

Abstract

A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of China application serial no. 201710256627.7, filed on Apr. 19, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTIONField of the Invention[0002]The invention relates to a semiconductor structure and a manufacturing method thereof; particularly, the invention relates to a memory having a shallow trench isolation (STI) structure and a manufacturing method of the memory.Description of Related Art[0003]As the level of integration of semiconductor devices increases, sizes of the semiconductor devices continuously decrease, thus leading to increasing mutual influence on the semiconductor devices. Generally, isolation structures are applied to isolate the semiconductor devices from one another, so as to avoid significant influences and improve the reliability of the devices. In memory ...

AI Technical Summary

Benefits of technology

The invention provides a memory structure and a manufacturing method that improves the performance and reliability of memory devices. The isolation structure has a recess therein, which shapes its top profile as a funnel. This results in improved protection of the sidewall of the first dielectric layer and avoidance of mutual interference during programming actions. Additionally, the recess in the isolation structure provides increased GCR, which further enhances the performance of the memory devices.

Problems solved by technology

In memory devices, the excessively small heights of the isolation structures may easily cause the mutual interference during programming actions and cause potential damages to tunneling dielectric layers, such that the reliability of the memory devices is deteriorated.

If the heights of the isolation structures are excessively large, however, the gate coupling ratio (GCR) may decrease, and thus the performance of the memory devices is lowered.

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