Method of fabricating non-volatile memory

Abstract

A method of fabricating a non-volatile memory includes providing a substrate having a composite dielectric layer, a sacrificial layer and a mask layer sequentially formed thereon. The mask layer is patterned to form a plurality of first openings for exposing a portion of the sacrificial layer. The sacrificial layer exposed by the first openings is removed and a plurality of first gates is formed in the first openings. The mask layer is further removed to form a plurality of second openings between the first gates. An insulating layer is formed on the tops and sidewalls of the first gates. A portion of the sacrificial layer exposed by the second openings is removed and a plurality of second gates is formed in the second openings. The second gates and the first gates embody a memory cell column. Source / region regions are formed in the substrate beside the memory cell column.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a fabrication method of a non-volatile memory.[0003]2. Description of Related Art[0004]In the various types of non-volatile memory, electrically erasable programmable read only memory (EEPROM) allows multiple data reading, writing and erasing operations. In addition, the stored data are retained even after power to the device is removed. With these advantages, electrically erasable programmable read only memories have been broadly applied in personal computers and electronic equipment.[0005]The industry provides a type of non-volatile memory as shown in FIG. 1. This non-volatile memory is constituted with a plurality of memory cells 102 and a plurality of memory cells 116. The memory cells 102 and the memory cells 116 are isolated from each other with the spacers 110. Each memory cell 102 is formed, sequen...

AI Technical Summary

Benefits of technology

The present invention provides a fabrication method for a non-volatile memory device that improves the reliability of memory cells and lowers the thermal budget. This is achieved by concurrently forming composite dielectric layers with the same properties to raise the reliability of memory cells. The method also reduces the manufacturing cost by lowering the thermal budget. The method includes forming sacrificial layers, a mask layer, and first and second openings. The sacrificial layers are removed to form the first and second gates, which form a memory cell column. The method also includes forming a second conductive layer over the substrate and removing a portion of the second conductive layer to expose the insulation layer at the tops of the first gates. The method further includes forming a mask layer and patterning it to form the first openings. The materials used in the composite dielectric layers, bottom dielectric layer, charge-storage layer, and top dielectric layer are silicon oxide and silicon nitride, respectively. The method also includes removing the mask layer to form the second openings. Overall, the method improves the reliability of memory cells, lowers the thermal budget, and reduces manufacturing costs.

Problems solved by technology

As a result, the fabrication process is complicated.

Consequently, the reliability of the memory cells is less desirable.

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