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DMOS transistor

a technology of mos and transistors, applied in the direction of transistors, electrical devices, semiconductor devices, etc., can solve the problems of deteriorating strength of dmos transistors, and achieve the effect of preventing deterioration of dmos transistor strength and reducing the resistance of dmos transistors

Active Publication Date: 2010-08-03
SEMICON COMPONENTS IND LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention provides a new structure for a DMOS transistor that reduces the ON resistance and prevents deterioration in strength against electrostatic discharge. This is achieved by placing a silicide layer on the surface of the source layer and not forming a silicide layer in the space between the source layer and the gate electrode. Additionally, the transistor has a structure that relaxes the electric field at the edge portion of the source layer and prevents the convergence of electric current.

Problems solved by technology

However, there is a problem that the silicide layer tends to cause convergence of an electric field and an electric current in the transistor and deteriorate strength of the DMOS transistor against electrostatic discharge, since the silicide layer is low in resistance.

Method used

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Embodiment Construction

[0015]A DMOS transistor according to an embodiment of this invention can be incorporated in an IC (Integrated Circuit) as a power semiconductor device such as a power supply circuit or a driver circuit. It realizes a low ON resistance (100 mΩ, for example), and is prevented from the deterioration in the strength against electrostatic discharge by forming a silicide layer using a silicidation technology so that the electric field and the electric current do not converge.

[0016]A structure of the DMOS transistor is hereafter described referring to the drawings. FIG. 1 is a plan view of the DMOS transistor according to the embodiment of this invention. FIG. 2 is a cross-sectional view showing a section X-X in FIG. 1. FIG. 3 is a cross-sectional view showing a section Y-Y in FIG. 1.

[0017]A silicon layer 2 of N− type is formed on a silicon substrate 1 of P type by epitaxial growth, as shown in the figures. It is preferable that a buried layer 3 of N+ type that is higher in impurity concen...

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Abstract

This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.

Description

CROSS-REFERENCE OF THE INVENTION[0001]This application claims priority from Japanese Patent Application No. 2008-109713, the content of which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a DMOS (Double-diffused MOS) transistor.[0004]2. Description of the Related Art[0005]The DMOS transistor is a MOS field effect transistor in which a source layer and a body layer that makes a channel are formed by double diffusion of impurities, and is used as a power semiconductor device for a power supply circuit, a driver circuit or the like.[0006]In recent years, because of requirements for electronic equipment such as mobile phones to reduce their size and power consumption, the DMOS transistor is required to reduce its ON resistance (a resistance of the DMOS transistor when it is turned on).[0007]Technologies to reduce the ON resistance and to improve a withstand voltage and the like of the DMOS tr...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L29/76H01L31/119H01L31/113H01L31/062H01L29/94H01L21/28H01L21/336H01L29/417H01L29/78
CPCH01L29/41758H01L29/41775H01L29/4238H01L29/7816H01L29/0878H01L29/456H01L29/4933H01L29/665H01L29/66689
Inventor OTAKE, SEIJIKIKUCHI, SHUICHITAKEDA, YASUHIROMAKI, KENICHI
Owner SEMICON COMPONENTS IND LLC