This invention discloses a method for manufacturing an inter-
gate dielectric layer of an SGT
semiconductor device, comprising: Step 1, forming a gate trench and a bottom
dielectric layer, wherein the bottom
dielectric layer covers the inner and outer surfaces of the gate trench. Step 2, forming a shielding gate conductive material layer and
etching back the shielding gate conductive material layer. Step 3, using the bottom
dielectric layer as a
mask, forming a first inter-
gate dielectric layer of desired thickness on the exposed top surface of the shielding gate conductive material layer. Step 4, forming a first
mask layer to protect the top region of the first inter-
gate dielectric layer. Step 5, performing a first
etching using the first
mask layer as a mask; after the first
etching, the bottom
dielectric layer located above the top surface of the shielding gate conductive material layer serves as a second inter-gate
dielectric layer. Step 6, removing the first
mask layer. Step 7, forming the gate
dielectric layer and the gate conductive material layer. This invention allows for independent adjustment of the thickness of the inter-gate dielectric layer with high quality and a simple process.