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Magnetic reluctance mode RAM circuit

A random access memory and magneto-resistive technology, which is applied in static memory, digital memory information, and magnetic field-controlled resistors, etc., can solve the problems of large storage array size, increased transistor area, and reduced MRAM storage array size.

Active Publication Date: 2008-04-02
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019] However, when the programming operation is performed in the above circuit, the programming current must flow through the transistors 52A and 52B. Since the programming current is quite large, the area of ​​the transistors 52A and 52B must be increased to withstand a large amount of programming current.
However, this will cause the size of the entire storage array to become larger, making the reduction of the size of the MRAM storage array encounter a technical bottleneck.

Method used

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Examples

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no. 1 example

[0051] FIG. 7 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to the first embodiment of the present invention. Wherein, W1-W3 and W1-W3 are word lines, P1-P4 are programming lines, and B1-B4 are bit lines.

[0052] The sources of the NMOS transistors 72A and 72B are respectively coupled to the free magnetic axis layer 102 of the magnetoresistive memory cells 70A and 70B, their gates are respectively coupled to the word lines W2 and W2, and their drains are respectively coupled to the bit Lines B3 and B2. In addition, the drains of the NMOS transistors 74A and 74B are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 70A and 70B, their gates are also respectively coupled to the word lines W2 and W2, and their sources are respectively coupled to Connect to programming lines P3 and P4. The programming lines P2 and P3 are respectively coupled to the fixed magnetic axis layer 106 ...

no. 2 example

[0056] FIG. 8 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a second embodiment of the present invention. Wherein, W1-W2 and W1-W2 are selection lines, and B1-B2 and B1-B2 are operation lines.

[0057] The drains of the NMOS transistors 82A and 82B are respectively coupled to the free magnetic axis layer 102 of the magnetoresistive memory cells 80A and 80B, the gates of which are both coupled to the selection line W2, and the sources are respectively coupled to the operating lines B2 and 80B. B1. In addition, the drains of the NMOS transistors 84A and 84B are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 80A and 80B, the gates of which are both coupled to the selection line W2, and the sources are also respectively coupled to the operation Line B2 and B1. The operation lines B1 and B2 are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistiv...

no. 3 example

[0061] FIG. 9 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a third embodiment of the present invention. Wherein, W1-W2 and W1-W2 are word lines, P1-P3 are programming lines, and B1-B2 are bit lines.

[0062] The sources of the NMOS transistors 92A and 94A are respectively coupled to the fixed magnetic axis layers of the magnetoresistive memory cells 90A and 90B, their gates are respectively coupled to the word lines W1 and W1, and their drains are respectively coupled to the programming line P1. with P2. In addition, the drains of the NMOS transistors 92B and 94B are respectively coupled to the fixed magnetic axis layers of the magnetoresistive memory cells 90A and 90B, their gates are also respectively coupled to the word lines W1 and W1, and their sources are respectively coupled to to programming lines P2 and P3. Here, the bit lines B1 and B2 are respectively coupled to the free magnetic axis layers of the magne...

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Abstract

A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Description

technical field [0001] The invention relates to a storage array, in particular to a storage array of a magnetoresistive random access memory. Background technique [0002] Magneto-resistive random access memory (Magnetic Random Access Memory, hereinafter referred to as MRAM) is a metal magnetic material, its radiation resistance is much higher than that of semiconductor materials, and it belongs to non-volatile random access memory (Non-volatile Random Access Memory) , when the computer is powered off or shut down, it can still maintain storage. [0003] MRAM uses magnetoresistance characteristics to store and record information, and has the characteristics of low energy consumption, non-volatility, and no limit on the number of reads and writes. The basic principle of its operation is the same as storing data on a hard disk. The data is stored as 0 or 1 based on the magnetic direction. The stored data is permanent and will not be changed until it is affected by an external...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/15H01L43/08G11C11/00G11C11/02G11C11/16H10N50/10
CPCG11C11/16
Inventor 林文钦邓端理池育德
Owner TAIWAN SEMICON MFG CO LTD