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Schockley barrier MOS transistor and its manufacturing method

A technology of MOS transistors and Schottky potential, which is applied in the field of Schottky barrier MOS transistors and its production, can solve the problems of device performance impact, thin silicon film thickness, poor interface, etc., to improve immunity and open state current, the effect of reducing the off-state current

Active Publication Date: 2008-05-21
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the thickness of the silicon film of the UTB structure device itself is too thin, and the process control is difficult to ensure the consistency of the whole chip; in addition, the interface between the silicon film and the buried oxygen of the SOI silicon wafer formed by SIMOX is relatively poor, which seriously affects the performance of the device. influences

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  • Schockley barrier MOS transistor and its manufacturing method
  • Schockley barrier MOS transistor and its manufacturing method
  • Schockley barrier MOS transistor and its manufacturing method

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Embodiment Construction

[0040] The following specific embodiments are helpful to understand the features and advantages of the present invention, but the implementation of the present invention is by no means limited to the described embodiments.

[0041] A specific embodiment of the manufacturing method of the present invention includes Figure 1 to Figure 6 Process steps shown:

[0042] 1. Such as figure 1 As shown, the SOI silicon wafer used uses a silicon substrate (1), the monocrystalline silicon film (3) on the buried oxide layer (2) has a crystal orientation of (100), and the silicon film is initially lightly doped. A conventional CMOS shallow trench isolation technology is used to fabricate the active region isolation layer (4).

[0043] 2. Such as figure 2 As shown, a gate oxide layer (5) is subsequently grown on the silicon film (3) and the isolation layer (4). The gate oxide layer is silicon dioxide with a thickness of 1 to 5 nm. The formation method of the gate oxide layer can be one of the ...

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Abstract

This invention provides a Schottky potential barrier MOS transistor characterizing that the source region and the drain region of said MOS transistor are composed of two layers of metals or compounds formed by metals and semiconductors, the process method of which is compatible with the traditional one and only adds the low energy ionic injection to increase the performance greatly.

Description

Technical field: [0001] The invention belongs to the technical field of semiconductor integrated circuits and their manufacturing, and particularly relates to a Schottky barrier MOS transistor with a new structure and a manufacturing method thereof. Background technique: [0002] The Schottky S / D structure was proposed by Lepselter and Sze in the late 1960s. They proposed to use metal (or silicide) to replace the traditional source and drain doping for the source and drain of the device. A Schottky barrier is formed between the metal (or silicide) and the silicon channel. The conduction of the device is carried out by the source terminal. The sub-tunnel directly through the barrier to achieve. Compared with traditional source-drain doped MOSFETs, Schottky S / D MOSFET has the following advantages. First, because the source and drain use high-conductivity metal or metal silicide, the parasitic resistance of Schottky source and drain is much smaller than that of doped source and drai...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/812H01L21/338
Inventor 李定宇孙雷张盛东刘晓彦韩汝琦
Owner SEMICON MFG INT (SHANGHAI) CORP