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Semiconductor back-end linked thread using glass contained F-Si as dielectric substance

A dielectric and semiconductor technology, applied in the field of semiconductor back-end wiring, can solve problems such as peeling, short electromigration life, electromigration failure, etc., and achieve the effects of good integrity, high product qualification rate, and improved electromigration life

Active Publication Date: 2008-09-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] But, there is following problem in the technological method of prior art: at first, as image 3 As shown in the mark A of b, the in-situ grown pad oxide layer has a thickness smaller than the nominal value at the corner of the line due to its poor conformality, which will seriously damage the integrity of the metal line during the subsequent FSG deposition process, as image 3 The sign of c is shown in B
[0005] Secondly, in order to maintain the integrity of the metal lines, the pad oxide layer grown in-situ must exceed a certain thickness, but this will cause a decrease in filling performance and leave small voids between the metal lines, which will cause problems in the subsequent manufacturing process. Causes potential metal growth in between, causing leakage between metal lines, which greatly reduces the yield; in addition, due to its high dielectric constant relative to FSG, the parasitic capacitance between metal lines increases, reducing the speed of the final circuit
[0006] Third, due to its low refractive index, the pad oxide layer grown in situ cannot well prevent the F element in FSG from diffusing to the interface between the dielectric and the metal, resulting in electromigration failure and reliability problems
[0007] Finally, during the sintering process of the alloy at about 400 degrees, there is no or only a layer of silicon oxide with a normal refractive index covering the FSG, which causes the F element in the FSG to diffuse upward from the FSG body to the interface with Ti, forming the fluorine of Ti compound, which reduces the bonding force, causing peeling between the dielectric material and the metal aluminum alloy line, resulting in low yield and electromigration failure
[0008] The methods in the prior art have problems such as incomplete metal lines, large parasitic capacitance, and peeling between the FSG and the film after the final high-temperature annealing, resulting in low product qualification rate and short electromigration life.

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  • Semiconductor back-end linked thread using glass contained F-Si as dielectric substance
  • Semiconductor back-end linked thread using glass contained F-Si as dielectric substance
  • Semiconductor back-end linked thread using glass contained F-Si as dielectric substance

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Embodiment Construction

[0019] like figure 2 , Figure 4 As shown, first, metal lines are formed, see Figure 4 a; Secondly, an oxide with a refractive index greater than 1.48 grown by plasma-enhanced chemical vapor deposition in PECVD equipment is used as a pad oxide layer, see Figure 4 b; wherein, the pad oxide layer is silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, and the film thickness of the pad oxide layer is greater than 12nm and less than 80nm. The third step is to use high-density plasma chemical vapor deposition to grow FSG and deposit FSG as a dielectric, see Figure 4 c; the fourth step, after the growth of the FSG dielectric, cover its surface with a layer of silicon oxide or tetraethoxysilane with a normal refractive index, and then use chemical mechanical polishing to planarize it, see Figure 4 d. In this step, it is also possible not to cover silicon oxide or tetraethoxysilane, and directly use chemical mechanical polishing to planarize it; the fi...

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Abstract

This invention discloses one semiconductor back end connection by use of fluorine-containing silicon glass as medium, which comprises the following steps: a, forming metal lines; b, growing oxidation with high reflection rate as underlay oxidation layer; c, depositing FSG as medium to cover one layer of normal reflection rate silicon oxidation or tetraethoxysilane; d, flattening the compound film by FSG, silicon oxidation or tetraethoxysilane; e, growing one layer of high reflection oxidation as cover layer in flatter silicon surface; f, opening hole as tungsten plug; g, removing redundant tungsten and diffuse block layer; h, depositing one layer of metal.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric. Background technique [0002] With the further development of semiconductor technology, nanotechnology is becoming more and more important, which also puts forward new requirements for the integration of subsequent processes. In the case of nanometer technology, it is necessary to further reduce the circuit delay caused by the parasitic capacitance of the subsequent metal interconnection and dielectric. Therefore, in the prior art, a new low-resistance material copper and a low-permittivity dielectric material such as FSG, that is, fluorine-containing silicon glass, are used in the semiconductor back-end wiring process. [0003] In the prior art, the schematic diagram of the semiconductor back-end wiring method using fluorine-containing silicon glass as the dielectric is sho...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/31
Inventor 陈俭田明刘春玲施红李菲陆涵蔚
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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