Method for simulating grid root deficiency and MOSFET device performance coherence

Abstract

A method for simulating correlation of grid root defect to MOSFET component performance includes setting simulation parameters based on product requirement and actual process parameter, using TCAD tool to simulate preparation process of semiconductor corresponding to grid root defect and using TCAD tool to analogize component physical character to obtain component character parameter response value series corresponding to grid root defect then obtaining function relation of grid root defect to component character parameter according to grid root defect and component character parameter response value series data obtained by simulation.

Description

technical field [0001] The invention relates to device simulation technology, in particular to a simulation method for correlation between gate root defect and MOSFET device performance in semiconductor manufacturing process. Background technique [0002] Metal-oxide-semiconductor field effect transistor (MOSFET) is a voltage control device, which controls the change of output current through input voltage, and is currently widely used in various electronic circuits. Taking the N-channel enhancement MOSFET as the representative structure, the working principle of the MOSFET is as follows. [0003] figure 1 It is a schematic diagram of the N-channel enhancement MOSFET structure; such as figure 1 As shown, the middle part of the MOSFET is a MOS capacitor structure composed of metal-oxide-semiconductor, and the oxide plays an insulating role between the metal and the semiconductor; the metal electrode on the insulating layer 40 is called the gate 20G, and the two sides of the...

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Problems solved by technology

[0005] figure 2 It is a schematic cross-sectional view of the gate root defect; the method described in the patent application with the application number "200310109108.6" mentions that in the actual production process, due to improper control of exposure, development or etching processes, the pattern of the gate 20 is likely to be incomplete, resulting in root defects of 60 such as figure 2 As shown, and this root defect 60 cannot be eliminated in the subsequent production process; the effect of this gate root defect can easily cause the performance reduction of MOSFET devices, such as the decrease of drain saturation current, the decrease of threshold voltage, the increase of interjunction capacitance, etc.; How to determine the degree of influence of root defects 60 on the performance of MOSFET devices has become an important problem faced by those skilled in the art

Using traditional experimental methods will not only consume a lot of manpower and material resources, but also require a long R&D cycle, which is not conducive to the normal production. Therefore, there is an urgent need for a process control window that can provide the root defect effect of the MOSFET gate, and can effectively A simulation method to guide the design of the process scheme and the production operation

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