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Semiconductor encapsulation structure possessing support part, and preparation method

A packaging structure, semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device parts, etc., can solve problems such as poor control of connection distance, excessive solder volume, short circuit of solder materials, etc., to avoid Effect of too low height of conductive adhesive material

Active Publication Date: 2009-01-28
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In order to solve other problems of the above-mentioned prior art, the main purpose of the present invention is to provide a semiconductor package structure with a support portion and its manufacturing method. The distance between the package structure and the external device is poorly controlled or the amount of solder is too much to avoid Cause the solder materials to contact each other and cause short circuit problems

Method used

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  • Semiconductor encapsulation structure possessing support part, and preparation method
  • Semiconductor encapsulation structure possessing support part, and preparation method
  • Semiconductor encapsulation structure possessing support part, and preparation method

Examples

Experimental program
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Embodiment 2

[0037] Figure 5A to Figure 5D A schematic cross-sectional view of Embodiment 2 of the method for manufacturing a semiconductor package structure with a support portion according to the present invention is shown. Similar to the above-mentioned manufacturing method, embodiment 2 is mainly to form the concave portion on the surface of the carrier before the electroplating process.

[0038] like Figure 5A As shown, firstly, a metal carrier 40 is provided, and a concave portion 43 is formed on the surface of the carrier 40 at a position where the circuit layout is not affected.

[0039] like Figure 5B As shown, a resist layer 41 is covered on the carrier, and the resist layer 41 covers the recess 43, and a plurality of openings are formed through a patterning process, so as to expose part of the carrier 40; then, an electroplating process is performed, The electroplating current is conducted through the metal carrier 40 , so as to form a plurality of electrical contacts 421 a...

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PUM

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Abstract

The structure includes multiple electrical contacts; at least one chip, and the chip is connected to the electrical contact; an encapsulation colloid in use for cladding the chip and electrical contacts. At least one surface of the multiple electrical contacts can be exposed out of the encapsulation colloid. Outward extended bulge is formed on the encapsulation colloid. Through the bulge, the encapsulation structure is connected to and placed on outer device. The invention prevents short circuit issue caused by inter contact of conducting sticky material on each electrical contact of encapsulation structure. Bearing height of bulge prevents too large thermal stress and break at sticky point caused by not high enough of conducting sticky material between encapsulation structure and outer devices.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure with a support portion and a manufacturing method thereof. Background technique [0002] A traditional semiconductor chip uses a lead frame as a chip carrier to form a semiconductor package. The lead frame includes a chip seat and a plurality of pins formed around the chip seat. After the semiconductor chip is bonded to the chip seat and the chip and the pins are electrically connected by welding wires, the package resin is used to cover the lead frame. The chip, the chip pad, the bonding wire and the inner section of the pin form the semiconductor package with the lead frame. [0003] There are many types and types of semiconductor packages with lead frames as chip carriers, such as QFP semiconductor packages (Quad Flat Package), QFN (Quad-Flat Non-leaded) semiconductor packages, SOP semiconduct...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L23/48H01L23/28
CPCH01L24/97H01L2924/18165H01L2224/48091H01L2224/16245H01L2224/73265H01L2924/18301H01L2224/48247H01L2924/181H01L2924/351H01L2924/00014H01L2924/00
Inventor 黄建屏汤富地
Owner SILICONWARE PRECISION IND CO LTD