Low-density odd-even checking codec hardware simulation system based on programmable gate array

A low-density parity, hardware emulation technology, applied in error detection coding using multi-bit parity bits, error correction/detection using block codes, special data processing applications, etc. problems such as rapid development problems, to achieve the effect of good noise quality, shortened simulation verification time, and good controllability

Active Publication Date: 2009-02-18
南京宁麒智能计算芯片研究院有限公司
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Problems solved by technology

[0004] At the same time, in the study of LDPC codes, the verification of LDPC decoders is also an important task. Since the verification work takes a lot of time, it also brings troubles to the rapid development of LDPC code research.

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  • Low-density odd-even checking codec hardware simulation system based on programmable gate array
  • Low-density odd-even checking codec hardware simulation system based on programmable gate array
  • Low-density odd-even checking codec hardware simulation system based on programmable gate array

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Embodiment Construction

[0022] The present invention will be described in further detail below in conjunction with the accompanying drawings. In the present embodiment, select the (2209,2021) Array LDPC code of code length N=2209 for use, the structure of this LDPC code is as attached Figure 5 shown. where I is the 47×47 identity matrix, α i is the matrix formed after the identity matrix I is shifted by i bits.

[0023] The input clock of the simulation system is 100MHz, and two clocks of 120MHz and 40Hz are obtained through processing by the digital phase-locked loop (DPLL) inside the FPGA. The entire FPGA hardware part operates at 40MHz except the decoder part, and the operating frequency of other parts is 120MHz.

[0024] figure 1 It is a structural schematic diagram of the FPGA-based LDPC codec hardware emulation system of the present invention, and the system includes a PC-side control software part and an FPGA-based hardware part. FPGA hardware part includes PCI interface control module a...

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Abstract

The invention discloses a kind of LDPC encode and decode hardware emulate system basing on FPGA. The system includes the control software of PC terminal and the hardware basing on DPFA which includes the control module of PCI interface, random number generator, Gaussian noise generator, LDPC encoder / decoder and so on. The invention bases on FPGA hardware and realizes simulation study of the LDPC, at the same time, the system is good at controllability, observation and reusability, and improves the pace of simulation ( is more than 300 times higher than the pace of the simulation software), offering a good lab environment for researching the same kind of error correcting codes further.

Description

technical field [0001] The invention belongs to the technical field of digital communication, and relates to a hardware simulation system applicable to the research of LDPC (Low-Density Parity Check, low-density parity check) codes and the verification of LDPC code decoders, specifically It is a low-density parity-check codec hardware emulation system based on programmable gate array. Background technique [0002] Among the currently existing coding methods, the LDPC coding method has shown coding performance close to the Shannon limit in some cases. LDPC codes have attracted worldwide attention due to their excellent performance, and are considered to be one of the promising error correction coding methods in communication system applications. The study of LDPC codes has become a research hotspot in the field of digital communication. [0003] At present, the research field of LDPC codes mainly revolves around two aspects: one is the design of the decoder; the other is th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50H03M13/11
Inventor 李丽张仲金高明伦何书专李伟董岚张川
Owner 南京宁麒智能计算芯片研究院有限公司
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