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Etching method and contact window forming method

A contact window and etching technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of the expansion of the anti-reflection layer of the photoresist layer, the failure of key dimensions to meet the requirements, and the decline in component reliability and other issues, to achieve the effect of improving the etching selectivity ratio, reducing the critical dimension, and improving the reliability

Active Publication Date: 2009-03-11
UNITED MICROELECTRONICS CORP
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  • Application Information

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Problems solved by technology

However, when etching in this way, it is easy to cause the problem of the expansion of the photoresist layer and the anti-reflection layer, so that the critical dimension of the opening after etching cannot reach the desired one.
On the other hand, this etching method has a limit for reducing the critical dimension after etching. Therefore, if the critical dimension cannot be effectively reduced, the distance between the formed contact openings will be too close, and even overlapping parts will appear, which is easy to This causes bridging of the contact window formed subsequently, which reduces the reliability of the component

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  • Etching method and contact window forming method
  • Etching method and contact window forming method
  • Etching method and contact window forming method

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Embodiment Construction

[0044] Figure 1A ~ Figure 1F A cross-sectional view of the manufacturing process of the contact window opening according to an embodiment of the present invention is shown. Figure 1A A metal oxide semiconductor device formed on a semiconductor substrate 100 is shown, and the metal oxide semiconductor device is isolated from other devices by an isolation structure 101 , such as a shallow trench isolation structure. The gate 104 of the metal oxide semiconductor device is formed on the gate dielectric layer 102 ; and the spacer 106 is formed on the sidewall of the gate 104 . The source region 108 and the drain region 110 are formed in the semiconductor substrate 100 on both sides of the gate 104 . In another embodiment, metal silicide 112 , such as nickel silicide, tungsten silicide or cobalt silicide, can be formed on the gate 104 , the source region 108 and the drain region 110 to reduce the resistance. The materials and forming methods of the above metal oxide semiconductor...

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Abstract

The related etching method comprises two steps, while the temperature on the second step is higher than the first. Thereby, this invention can form small final size.

Description

technical field [0001] The invention relates to an etching method, in particular to an etching method capable of reducing key dimensions. Background technique [0002] In the case of higher and higher requirements for integration, the design of the size of the entire semiconductor element is developing towards a reduction in size. The method of reducing the line pitch of the pattern in the integrated circuit process is mostly achieved by using a high-resolution photolithography process. However, the high-resolution photolithography process is technically difficult and expensive due to the inherent optical limitations. [0003] At present, there is an etching process method, which can achieve the purpose of reducing the critical dimension after etching without using a high-resolution photolithography process. This method uses the existing photolithography process to form the post-development inspection critical dimension (ADI CD), and then uses a polymer rich and low power ...

Claims

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Application Information

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IPC IPC(8): H01L21/30H01L21/311H01L21/3213H01L21/768H01L21/28C23F1/12
Inventor 周珮玉廖俊雄
Owner UNITED MICROELECTRONICS CORP