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Forming method of shallow plow groove isolation structure

An isolation structure, shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to reduce stress levels, optimize performance, and improve substrate surface stress levels

Inactive Publication Date: 2009-04-29
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, since the insulating medium filled in the trench by the HDP-CVD process is very dense, the insulating medium itself will generate a strong compressive stress (compressive strain), although the trench sidewall and liner material are different from the insulating medium filled in the trench. The stress between the dielectrics can be reduced or eliminated by the above methods, but the compressive stress generated by the insulating dielectric itself still exists, so that the shallow trench isolation structure presents a high compressive stress state

Method used

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  • Forming method of shallow plow groove isolation structure
  • Forming method of shallow plow groove isolation structure
  • Forming method of shallow plow groove isolation structure

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Embodiment Construction

[0038] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0039] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for forming a shallow trench isolation structure in a semiconductor device and the shallow trench isolation structure. It should be noted here that this specification provides different embodiments to illustrate the various features of the present invention, but these embodiments are only for convenience of description by using specific compositions and structures, and do not limit the present invention.

[0040] After the manufacturing process of semiconductor devices enters the process node of 65nm and below, the influence of stress on the carrier mobility of CMOS devices becomes more and more obvious. The ...

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Abstract

A forming method for the structure of the STI is provided, which comprises an underlay of semiconductor, etching the said underlay to form the groove; padding insulant into the groove and planarize the said groove; forming pad barrier layer on the underlay surface; forming single-layer or muti-layer stress thin film layer on the said pad barrier layer and the groove surface; heat annealing to the said pad; divesting the said stress thin film layer. The invention can efficiently control the stress of the STI structure and the underlay surface to improve the performance of the semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure in a semiconductor device. Background technique [0002] As semiconductor technology enters the deep submicron era, in components below 0.13 μm such as CMOS devices, the isolation between NMOS transistors and PMOS transistors is formed by shallow trench isolation (STI) technology. figure 1 A schematic diagram of the shallow trench isolation structure. In this process, shallow trenches are first formed on the substrate 100, and the elements are separated by etched trenches 130, and then a pad oxide layer 110 is formed on the side walls and bottom of the trenches, and chemical vapor deposition is used to Dielectric deposition (CVD) fills the shallow trenches with an insulating dielectric, such as silicon oxide. After the insulating medium is filled, a dense and hard silicon nitride etch stop layer 120 i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 刘明源
Owner SEMICON MFG INT (SHANGHAI) CORP
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