High-speed burst mode clock data recovery circuit

Abstract

The present invention proposes a high-speed burst mode clock and data recovery circuit, which is composed of an edge detection circuit 1, a current-limiting timer 2 with a trigger input, a frequency stabilization loop 3, and a judgment output circuit 4. On the premise that the peripheral frequency stabilization loop ensures that the recovery clock frequency is consistent with the input signal clock frequency, the trigger signal output by the edge detection circuit is used to controlly intervene in the oscillation state of the current-limiting timing circuit, so that the oscillation state is at the lowest level and maintained to the best decision moment; thereby realizing bit synchronization and fast data recovery. The circuit has the characteristics of simple structure, high reliability, fast synchronization rate and low cost, and is suitable for the development requirements of technology and market, and is easy to be integrated or re-integrated.

Description

technical field [0001] The invention belongs to the technical field of digital communication, and particularly relates to a high-speed burst mode clock data recovery circuit technology. Background technique [0002] DWDM (Dense Wavelength Division Multiplexing) technology provides a huge transmission capacity for the communication network, and gradually becomes the mainstream transmission technology. With the maturity of DWDM technology and the rapid growth of transmission capacity, the pressure on the traditional electronic switching system is increasing day by day, and the introduction of optical switching technology is increasingly urgent. From the perspective of supported business types, optical switching can be divided into circuit switching (wavelength routing) and packet switching. Optical logic devices are still immature and cannot complete complex logic processing functions, so they can only implement electronically controlled optical switching, that is, identify h...

AI Technical Summary

Problems solved by technology

Among these two burst mode synchronization methods, the correlation synchronization method cannot meet the clock and data recovery (CDR) requirements of high-performance communication systems due to the complexity of the system and the slow synchronization speed, and the R&D cost will increase due to the involvement of too many digital processing modules. very high

Although the improved gated oscillation method has a fast synchronization rate, it has extremely high requirements on the manufacturing process of the circuit, and its research and development costs are not affordable for general research and development units and the general civilian market.

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