Test method of semiconductor integrated circuit device

Abstract

A method for testing a semiconductor integrated circuit device, comprising: providing the above-mentioned semiconductor integrated circuit device having a logic circuit, the power supply voltage of which is a first voltage when the logic circuit operates normally; and applying a substrate voltage to the MOS transistor of the logic circuit. a bias voltage to increase the threshold voltage of the MOS transistor; applying a second voltage lower than the first voltage to the logic circuit as a power supply voltage of the logic circuit; and when the transistor of the logic circuit is in a static state, The power supply current of the above semiconductor integrated circuit device was measured.

Description

[0001] This application is a divisional application of the invention patent application with the application number 99118577.3 and the invention name "semiconductor integrated circuit device" submitted by Hitachi Manufacturing Co., Ltd. on September 9, 1999. technical field [0002] The present invention relates to a test method for a semiconductor integrated circuit device, and more particularly to a test method for a semiconductor integrated circuit device having both high speed and low power. Background technique [0003] CMOS circuits come with low voltage speed drops. In order to compensate for the speed drop, the threshold voltage of the MOS transistor (or MIS transistor) must be lowered. However, there is a problem that the power consumption when the CMOS circuit is not operating is increased due to the subthreshold leakage current of the MOS transistor. One solution to this problem is described, for example, in IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, N...

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Problems solved by technology

[0016] In this way, it was found that in a MOS with a thin oxide film, applying a substrate bias to a depth greater than a certain level cannot reduce the leakage current as previously thought, and the leakage current at turn-off increases due to GIDL.

Although it depends on the cross-section of the transistor (for example, the impurity concentration of the diffusion layer, etc.), in a MOS transistor with an oxide film thickness of less than 5nm, since the value of the GIDL current reaches a value that cannot be ignored, the range of the substrate bias that can be applied restricted

Therefore, in the technique of the conventional example, the effect of reducing the leakage current has to be limited in the MOS transistor with a thin oxide film thickness.

[0017] (4) Due to sub-threshold leakage current and pn junction leakage current, it is difficult to test the failure judgment of the circuit with the current value flowing in the circuit

[0020] (2) As the drain voltage decreases, the threshold voltage of the MOS transistor increases due to the drain-induced barrier lowering effect (DIBL)

In this disclosure example, it is not recognized that the multiplication of the above methods can effectively reduce the leakage current in thin film transistors, and only discloses that the conventional substrate bias voltage can be changed by controlling the substrate bias voltage and power supply voltage. Variation

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