Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. In a conventional semiconductor device, because the horizontal diffuse width of a P type embedding diffuse layer which constitutes a separating region become wider, desired anti-pressing characteristic is difficult to be obtained. In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

Description

technical field [0001] The present invention relates to a semiconductor device that maintains withstand voltage characteristics and reduces the size of the device and its manufacturing method. Background technique [0002] As an example of a conventional semiconductor device, the structure of the NPN transistor 61 described below is well known. Such as Figure 9 As shown, an N-type epitaxial layer 63 is formed on a P-type semiconductor substrate 62 . On the epitaxial layer 63 are formed P-type buried diffusion layers 64 and 65 diffused upward and downward (depth direction) from the surface of the substrate 62 and P-type diffused layers 66 and 67 diffused from the surface of the epitaxial layer 63 . Further, the epitaxial layer 63 is divided into a plurality of element formation regions by the isolation regions 68 and 69 formed by connecting the P-type buried diffusion layers 64 and 65 to the P-type diffusion layers 66 and 67 . On one element forming region, for example, an...

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Problems solved by technology

Therefore, since the lateral diffusion widths W4, W5 of the P-type buried diffusion layers 64, 65 become wider, there is a problem that it is difficult to reduce the device size of the NPN transistor 61.

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