Variable gain high sensitivity GPS receiver baseband frequency tracking method

[0017] Figure 1 is a block diagram of the carrier tracking loop in the present invention. The meanings of the signals in the figure are as follows. 101 is the output of the Prompt Correlator in the traditional GPS receiver. The signal can be obtained from the hardware register by means of interrupt or software query. The new output value 101 of the correlator obtained each time is sent to a four-quadrant arctangent frequency discriminator and a four-quadrant arctangent phase discriminator, and the frequency error estimation signal 102 and the phase error estimation signal 103 can be obtained respectively. 102 and 103 After the loop filter is processed, the control signal 104 of the digital control oscillator is obtained, which controls the frequency of the local reproduced carrier generated by the digital control oscillator, and 105 is the output signal of the digital control oscillator.

[0018] Figure 2 is a schematic diagram of a method for GPS signal carrier tracking using the solution provided by the present invention.

[0019] When the GPS signal carrier is tracked after the GPS signal is correctly captured and before the data is demodulated, 1) A phase-locked loop assisted by the frequency-locked loop is used to realize the initial tracking of the GPS signal carrier, and the frequency discriminator gains Choose a higher value but not too large. The gain of the digitally controlled oscillator is slightly less than 1, and the loop will go to the second step after the loop has been working for a preset period of time;

[0020] 2) Continue to use the above-mentioned loop for tracking and use the histogram method for bit synchronization. The selection of the frequency discriminator gain and digital control oscillator gain in this stage is lower than the previous stage;

[0021] 3) Continue the above tracking process, and use the same method to perform bit synchronization again. After a period of time, the position of the maximum value in the histogram is taken as the starting position of a bit period, if the maximum value appears in the first position of the histogram It is considered that the bit synchronization is successful, otherwise it is considered that the bit synchronization is failed. If the bit synchronization is successful and the lock indicator shows that the carrier is locked, the conventional demodulation method can be used to demodulate the data, otherwise the GPS signal capture is performed again. At this stage, the gain of the frequency discriminator and the digital control oscillator are both less than 1, but still 10 -1 Magnitude.

[0022] 4) Judge whether the loop is locked, and if it is successfully locked, it will be transferred to data demodulation. Otherwise, the GPS signal can be re-acquired by conventional methods.

[0023] The first 3 steps determine a working state of the loop, and there are three states in total. The entrance of each state is to detect whether there is new data output in the Prompt road of the correlator, and if there is, judge the working state of the loop and transfer to the corresponding processing module. The duration of each state is determined by three preset time thresholds (for example, the working time of the three states can be set to 2 seconds). In each state, the loop completes frequency offset correction through the FLL-assisted PLL. The end of loop state three marks the completion of step three, and then step four is used to determine whether the loop is locked. The specific implementation process is as follows:

[0024] (1) Judge whether there is new data generated, and if so, judge the loop state. When the loop is in the state, the frequency offset correction is completed through the FLL-assisted PLL. At this time, the gain of the frequency discriminator and the gain of the digitally controlled oscillator are relatively higher than the other two working states. For example, the gain of the frequency discriminator and the gain of the digitally controlled oscillator can be set to 1 or more. After the required operation is over, it is judged whether the specified working time has been reached. If the specified working time is reached, it will switch to state two when new data is generated, otherwise it will continue to work in state two and wait for the generation of new data. When the state is over, the residual frequency deviation of the system can be reduced to within plus or minus 10 Hz.

[0025] (2) Judge whether new data is generated, and if so, judge the loop state. When the loop is in state 2, it is necessary to reduce the gain of the discriminator and the digital control oscillator (for example, it can be reduced to about 0.5), and continue to complete the frequency offset correction through the FLL-assisted PLL. Use the histogram method for bit synchronization. Determine whether and reach the specified working hours. If the specified working time is reached, the position of the maximum value in the histogram is obtained, the millisecond count is corrected according to the position of the maximum value, and the state 2 is finally ended and the state 3 is transferred after the new data is generated. If it does not reach the specified time, continue to work in state two and wait for the generation of new data.

[0026] (3) Judge whether new data is generated, and if so, judge the loop state. When the loop is working in state three, it is necessary to reduce the gain of the discriminator and the gain of the digital control oscillator again. At this time, both gains are 10 -2 Magnitude. Frequency offset correction is done through FLL-assisted PLL. Perform the second bit synchronization and take out the position of the maximum value in the histogram when the specified working time is reached. If the maximum position is 1, it is considered that the bit synchronization is successful, otherwise it is considered that the bit synchronization has failed. If the bit synchronization is successful and the carrier lock indicator shows that the carrier has been locked, it can be transferred to the data demodulation process. If the bit synchronization fails or the carrier lock indicator shows that the carrier is not locked, the GPS signal is captured again. If the specified working time is not reached, continue to work in state three and wait for the generation of new data.

[0027] (4) If it is determined that the GPS signal has not been captured correctly at the end of the third state, the conventional method is used to capture again.