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Delay locked loop having charge pump gain independent of operating frequency

A delay-locked loop, charge pump technology, applied in the direction of automatic power control, electrical components, etc., can solve problems such as large voltage swing values

Inactive Publication Date: 2010-08-11
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the period of the clock signal becomes longer (lower frequency), the magnitude of the voltage swing on the control node of the voltage-controlled delay line Vc becomes larger and thus more jitter is generated on the output of the delay chain 12

Method used

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  • Delay locked loop having charge pump gain independent of operating frequency
  • Delay locked loop having charge pump gain independent of operating frequency
  • Delay locked loop having charge pump gain independent of operating frequency

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Embodiment Construction

[0020] FIG. 2 depicts a delay-locked loop (DLL) circuit 20 that is similar to an implementation of the prior art circuit shown in FIG. Cycle time provides charge. The switched capacitor charge pump 28 includes an input 38 coupled to the output of a phase detector (PD) 14 and an output 40 coupled to a capacitive load 18 on a voltage controlled delay line Vc.

[0021] FIG. 3 depicts a schematic diagram of an exemplary switched capacitor charge pump 28 comprising: a charge / dump signal generation stage 30 ; a pair of switched capacitor stages 32 , 34 ; and an output stage 36 .

[0022] The charge / dump signal generation stage 30 takes as input a reference clock 50 and a phase-shifted reference clock 52 and outputs a charge signal 54 and a dump signal 56 during each cycle of the reference clock 50 . FIG. 4 illustrates a waveform diagram for generating charge signal 54 and dump signal 56 . The waveform diagram of FIG. 4 includes a reference clock 50 , a 270 degree phase shifted ref...

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Abstract

The present invention provides a delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A charge pump is disclosed for providing a charge to a capacitive element on a voltage controlled delay line, wherein the charge is independent of a control voltage step cycle time of the DLL, the charge pump includes: a charge / dump signal generation stage that generates a charge signal and a dump signal during each period of a reference clock signal; a first switched capacitor stage that charges a first capacitor in response to the charge signal and dumps a positive charge from the first capacitor in response to the dump signal; a second switched capacitor stage that charges a second capacitor in response to the charge signal and dumps a negative charge from the second capacitor in response to the dump signal; and an output stage that selectively loads either the positive charge or the negative charge to the capacitive element on the voltage controlleddelay line in response to an input signal from a phase detector.

Description

technical field [0001] The present invention relates generally to delay locked loops (DLLs), and more particularly to using switched capacitor circuits as charge pumps to eliminate the dependence of the value of the control voltage step on cycle time. Background technique [0002] A delay-locked loop (DLL) is a common circuit used to synchronize clocks. DLLs work by inserting a delay between the input clock and the feedback clock until the two rising edges are aligned, making the two clocks 360° out of phase (meaning they are in phase, but delayed by exactly time of one clock cycle). The DLL "locks" after the edge from the input clock aligns with the edge from the feedback clock. As long as the circuit is not evaluated until after the DLL has locked, the two clocks have no discernible phase difference. [0003] A DLL typically includes a phase detector (eg, XOR latch, etc.), a charge pump, capacitors, and a voltage-controlled delay line. Typically, such phase detectors a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/085
CPCH03L7/0812H03L7/0893H03L7/0816
Inventor 查尔斯·J.·马塞纳斯
Owner INT BUSINESS MASCH CORP