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Method of designing semiconductor device

By balancing the occupancy of high-density areas and low-density areas in the semiconductor chip, dishing of the interlayer insulating film is suppressed and dummy interconnections are avoided, solving the problem of inaccurate detection of dishing and dry etching end points in semiconductor device production. problems and improve the performance and stability of the device.

Active Publication Date: 2007-11-28
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] As described above, when the dummy interconnection 8 is formed in order to suppress variation in interconnection density, the overall interconnection density is further increased, and thus the problem occurs in the dry etching process
In addition, when the dummy interconnection 8 is formed, there arises a problem that the interconnection capacitance increases

Method used

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Examples

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no. 1 example

[0036] FIG. 4 conceptually shows an example of a design target semiconductor device. A layout area LAY is defined corresponding to a chip (semiconductor chip 10 ) of a semiconductor device. Multiple interconnections are laid out in the layout area LAY.

[0037] In FIG. 4, the layout area LAY is divided into a high-density area RH and a low-density area RL. The interconnection density is relatively high in the high-density area, and the interconnection density is relatively low in the low-density area. Specifically, the high-density region RH is defined as a region where the interconnection density per unit area is higher than a predetermined reference value. On the other hand, the low-density region RL is defined as a region where the interconnection density per unit area is equal to or less than a predetermined reference value. For example, the predetermined reference value is set at 70%.

[0038] In this case, the occupancy OCC of the high-density region RH for the layout...

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Abstract

A method of designing a semiconductor device includes: dividing a layout region of a semiconductor chip into matrix by a unit region; and determining an interconnection layout such that an occupation ratio of a high-density region to the layout region is less than 50%. Here, the high-density region is a set of the unit regions in each of which interconnection density is higher than a predetermined reference value.

Description

technical field [0001] The present invention relates to a method of designing a semiconductor device. In particular, the present invention relates to a method of patterning interconnections in a semiconductor device. Background technique [0002] CMP (Chemical Mechanical Polishing) is known as a planarization technique employed in the production process of semiconductor devices. When forming a multilayer interconnection structure, CMP is used to planarize metal interconnections or to planarize an interlayer insulating film. [0003] For example, CMP is used when forming low-resistivity Cu (copper) interconnections by a method called a damascene process. More specifically, after forming a trench on the insulating film, Cu is deposited into the trench, and then excess Cu outside the trench is polished off by CMP. Here, in the case where the width of the formed Cu interconnection is large, there occurs a phenomenon called "disshing" in which the surface flattened by CMP beco...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50H01L27/02H01L23/522H01L21/82H01L21/768
CPCG06F17/5077G06F30/394
Owner RENESAS ELECTRONICS CORP