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Manufacturing method of floating grid and non-volatility memory

A manufacturing method and floating gate technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as process trouble and removal

Inactive Publication Date: 2008-02-06
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, the silicon dioxide filled in the trench will remain on the hard mask layer of the memory cell region, and cannot be removed by chemical mechanical polishing, which will cause troubles in subsequent processes

Method used

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  • Manufacturing method of floating grid and non-volatility memory
  • Manufacturing method of floating grid and non-volatility memory

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Experimental program
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Embodiment Construction

[0038] 1A to 1F are cross-sectional views showing the manufacturing process of the non-volatile memory according to the embodiment of the present invention. Please refer to FIG. 1A , the manufacturing method of the non-volatile memory, for example, firstly provides a substrate 100 , and sequentially forms a dielectric layer 110 , a conductive layer 120 and a mask layer 123 on the substrate 100 . Wherein, the substrate 100 is, for example, a silicon substrate. The material of the dielectric layer 110 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation or chemical vapor deposition. In an embodiment, the thickness of the dielectric layer 110 is about 120 Angstroms. The material of the conductive layer 120 is, for example, amorphous silicon, and its formation method is, for example, chemical vapor deposition. The material of the mask layer 123 is, for example, silicon nitride, silicon carbide or silicon carbide nitride, and its formation m...

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Abstract

The present invention relates to a manufacturing method for the floating grid, for example, the method is to provide a substrate firstly, on the substrate, a dielectric layer, a first conductor layer and a mask layer are formed. Inside the mask layer, the first conductor layer, the dielectric layer and the substrate, a plurality of separation structures are formed. Then, a part of the mask layer is removed step by step, the steps includes: a part of the mask layer is removed, and a part of the separation structure is removed, the top surface of the separation structure is higher than that of the first conductor layer, then, the rest of mask layer is removed. Furthermore, a second conductor layer is formed on the substrate, the spaces between the separation structures are filled well.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor element, in particular to a manufacturing method of a floating gate and a non-volatile memory. Background technique [0002] Among all kinds of non-volatile memory products, it has the advantages of multiple data storage, reading, erasing, etc., and the stored data will not disappear after power off. Program read-only memory (EEPROM) has become a non-volatile memory widely used in personal computers and electronic equipment. [0003] A typical EEPROM uses doped polysilicon to make a floating gate and a control gate. Generally speaking, the greater the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the operating voltage required for its operation, and the operating speed and efficiency of the memory will decrease with the increase of the gate-coupling ratio (GCR). The improvement. Since the gate coupling ratio refers to the ratio of the capacitance...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336H01L21/8247
Inventor 何青原林锡坚萧国坤
Owner POWERCHIP SEMICON CORP