Method of manufacturing semiconductor device and dynamic random access memory

Abstract

A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source / drain region located within the recessed region and one source / drain region located out of the recessed region, a storage device connected to the source / drain located out of the recessed region, and a bit line connected to the source / drain located within the recessed region.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to a semiconductor device having a step gate. Background technique [0002] In order to increase the stacking density of devices in DRAM and improve its overall performance, current manufacturing technology continues to strive towards reducing the size of capacitors and transistors in DRAM. However, as the size of the transistor in the memory cell shrinks, the standard channel length of the transistor (ie, the line width of the gate) also shrinks. A shorter channel length will more easily lead to the occurrence of the so-called "short channel effect (SCE)" and the generation of higher subthreshold leakage current (subthreshold leakage) of the transistor in the memory cell, and eventually will degrade the performance of the memory cell. [0003] Various methods for overcoming the aforementioned problems have been developed. One of the methods for suppressing the short chann...

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Problems solved by technology

However, when the size of the transistor is reduced, the above methods cannot effectively minimize the problems of short channel effect and subthreshold leakage current, even at a very low doping concentration.

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