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Measurement apparatus for improving performance of standard cell library

A standard cell library, measuring device technology, applied in the direction of measuring device, measuring electricity, measuring electrical variables, etc., can solve the problems of difficulty in obtaining the standard deviation and average of traditional ring oscillators, increasing chip size, and measuring errors.

Inactive Publication Date: 2008-12-31
DONGBU HITEK CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0044] In Figure 4, since the application time of the second enable signal does not have the same ratio to the oscillation period of the ring oscillator, even at the application time of the same enable signal may occur corresponding to one oscillation period of the ring oscillator measurement error
[0045] Additionally, it is difficult to obtain the standard deviation and mean of measurements of traditional ring oscillator performance and the delta values ​​associated with the mean
[0046] In addition, conventional measurement devices require a separate register bank or multiple flip-flops to set the operating time of multiple ring oscillators and set the initial value of counters used for performance measurement, thereby increasing the overall chip size

Method used

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  • Measurement apparatus for improving performance of standard cell library
  • Measurement apparatus for improving performance of standard cell library
  • Measurement apparatus for improving performance of standard cell library

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Embodiment Construction

[0073] Reference will now be made in detail to the preferred embodiments of the invention in association with cold cathode fluorescent lamps, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to designate the same or like parts. In the following description of the present invention, when a detailed description of known functions and structures incorporated therein may make the subject matter of the present invention more unclear, it will be omitted.

[0074] FIG. 5 is a block diagram showing the structure of a built-in device for measurement of ring oscillator performance according to one embodiment of the present invention.

[0075] Referring to FIG. 5, the measuring device according to the present invention is a built-in type.

[0076] The measurement device according to the invention comprises a plurality of ring oscillator blocks 401 , a decoder 402 and a statistics aid 403 .

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Abstract

The invention discloses a measurement apparatus for improving performances of standard cells in a standard cell library when verifying performance of the standard cell library through a ring oscillator among various test element groups (TEGs). A built-in circuit is used to measure and verify performance of the standard cell library through a TEG. Therefore, it is possible to effectively improve performances of the standard cells in the standard cell library. Particularly, it is possible to not only remove human errors or internal errors of equipment, but also perform the measurement more readily, rapidly and accurately. Further, it is possible to curtail the use of high-performance equipment or manpower and time required in a measurement process.

Description

[0001] This application claims priority from Korean Patent Application No. P2007-0062702 filed on June 26, 2007, the entire contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to checking the performance of standard cell library by test element group (test element group, TEG), more particularly, relates to a kind of measuring device, when using ring oscillator in different TEG to check the performance of standard cell library The measurement device is used to improve the performance of standard cells in a standard cell library. Background technique [0003] figure 1 is a block diagram showing the structure of a conventional ring oscillator. [0004] Typically, a ring oscillator is composed of a plurality of delay chains 102 to 103 . Such as figure 1 As shown in , a delay chain 102 has a NAND gate 101 and a series of inverters IV-1 to IV-N. That is, the delay chain 102 includes a NAND gate 101, a first inverter IV...

Claims

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Application Information

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IPC IPC(8): G01R31/00
CPCG01R31/318594H03K3/03G11C29/12
Inventor 金成轩申又澈赵敬淳
Owner DONGBU HITEK CO LTD
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