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Method of manufacturing mask for semiconductor device

A semiconductor and mask technology, used in semiconductor/solid-state device manufacturing, originals for opto-mechanical processing, and photolithography processes for patterned surfaces, which can solve the degradation of wafer yield, the impact of production time, and the increase in time consumption and cost. And other issues

Inactive Publication Date: 2008-12-31
DONGBU HITEK CO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0021] If abnormal OPC operation on a recessed pattern produces a pattern with weak resistance to bridging or local shrinkage, the process margin becomes insufficient
In particular, in a relatively unstable portion such as the edge portion of the wafer, the yield of the entire wafer may be degraded due to disconnection and / or shorting of metal lines
[0022] Also, in order to accurately realize complex patterns, the photomask cost is increased due to the increase in time and consumption cost for testing and repairing the performance of photomask manufacturing equipment
Delays in transition to wafer process due to correction of reticle errors lead to delays in all steps of the scheme and thus have an impact on market production time (e.g. market supply and market margins)

Method used

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  • Method of manufacturing mask for semiconductor device
  • Method of manufacturing mask for semiconductor device
  • Method of manufacturing mask for semiconductor device

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Embodiment Construction

[0038] Preferred embodiments and examples of the present invention will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0039] Figure 4 is a flowchart illustrating an exemplary method of fabricating a mask using optical proximity correction a1 (OPC). First, a design database input step (S402) is implemented to input the design database into the mask manufacturing process. For example, after tape-out, the design database can be transferred to a semiconductor manufacturing facility (FAB) to implement the process based on the FAB's manufacturing capabilities.

[0040] Implement the design rule detection (DRC) step (S404), whether the input data of detection layout exceeds (drawn) the design rule that follows, if find the design error against this design rule or implement the layout correction step (S406) that violates the rule and correct...

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Abstract

A method of manufacturing a mask for a semiconductor device includes checking layout data for a mask in the semiconductor device and correcting any errors in the layout data that violate the design rule, filling small jogs in the layout data, performing optical proximity correction on the jog-filled layout data, and generating a mask pattern using the jog-filled layout data subjected to the optical proximity correction. By this process, it is possible to simplify the layout database to be subjected to optical proximity correction and minimize any errors that may cause unnecessary optical proximity correction (OPC) issues.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2007-0062846 (filed on June 26, 2007), the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a method for manufacturing a mask for a semiconductor device, and more particularly, to a method for converting layout data (layout date) into ) pattern data, implement OPC on the layout data, and form a mask pattern. Layout data is generally considered to be fundamental data for mask generation. Background technique [0003] In nanoscale semiconductor fabrication processes, problems associated with fabrication, lithography, and / or other process variations can affect the performance of semiconductor devices. Accordingly, there is a need to have accurate information for reliably estimating the effects of distortion and / or other process variations on semiconductor designs. Generally, a semiconductor integrated circuit (IC) manufacturing ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/14G03F1/00
CPCG03F1/36H01L21/0274H01L21/0337
Inventor 金英美
Owner DONGBU HITEK CO LTD