Semiconductor device and manufacturing method of the same

Abstract

In J-FET, since the impurity concentration of a channel region is lower than that of a gate region and a back gate region, p type impurity form the gate region and the back gate region diffuses such that n type impurity from the channel region below a gate region has a decreased concentration, thus resulting in the problems of deterioration of the forward transfer admittance gm and increase of the voltage gain Gv, and increase of the noise voltage Vno, which are caused by the IDSS variation and increase of the resistant of the current path. An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

Description

technical field [0001] The present invention relates to a semiconductor device used in high-frequency equipment and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof that reduce deviation and noise of IDSS. Background technique [0002] Figure 10 It is a cross-sectional view showing an example of a junction field effect transistor (Junction FET (Field Effect Transistor): hereinafter referred to as J-FET) 200 used in a conventional high-frequency device. [0003] For example, a p-type semiconductor layer 22 is laminated on a p-type silicon semiconductor substrate 21 to form a semiconductor substrate 20, and the surface of the semiconductor substrate 20 is provided with an n-type semiconductor layer divided by a high-concentration p-type impurity region, that is, a separation region 23. The channel region 24. An n + -type source region 25 and a drain region 26 are provided in the n-type channel region 24 , and ...

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Problems solved by technology

[0016] However, setting the channel region to a high concentration means that the impurity concentration around the side of the gate region is also increased, that is, the source-gate is applied The expansion of the depletion layer is insufficient when the VGSO is reverse-biased, and there is a problem that the specified withstand voltage cannot be ensured.

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