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Program execution control device

A control device and program execution technology, applied in the direction of program control design, machine execution device, concurrent instruction execution, etc., can solve the problems such as the increase of circuit scale and loss of effectiveness, and achieve the goal of suppressing performance deterioration, improving performance, and reducing circuit investment. Effect

Active Publication Date: 2013-05-22
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the table is used, the required circuit scale becomes larger
[0024] In this way, the last round of predictive control using the loop counter was effective in the traditional DSP field in the past. However, in the current high-performance processors premised on large-scale software development, from the perspective of its applicable objects, software production performance and hardware investment point of view, loses effectiveness

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0059] image 3 It is a structural block diagram of the processor related to Embodiment 1 of the present invention.

[0060] The processor is a device that executes a program, and includes an instruction fetching device 31, an instruction memory 32, an instruction decoding device 33, an instruction execution device 34, a register file 35, a data memory 36, a predicate tag control device 37, and a loop branch prediction device 38.

[0061] The instruction memory 32 is a type of memory that stores multiple instructions constituting a program. The instruction acquisition device 31 is a processing unit that acquires instructions stored in the instruction memory 32. The instruction acquisition device 31 sends the instruction acquisition address to the instruction memory 32, and the instruction acquisition address is the address of the instruction stored in the instruction memory 32. The instruction memory 32 sends the instruction stored in the received instruction acquisition address t...

Embodiment 2

[0132] The feature of the second embodiment is that the power state is changed for the processing state of the processor.

[0133] Figure 18 It is a structural block diagram of a processor related to Embodiment 2 of the present invention. Among the processors involved in embodiment 2, except image 3 The configuration of the processor according to the first embodiment shown further includes a power control device 71.

[0134] The processing performed by the processing unit other than the power control device 71 is the same as in the first embodiment. Therefore, detailed description will not be repeated here.

[0135] The power control device 71 performs power control based on the information of the last cycle mark. Figure 19 An example of the configuration of the power control device 71 is shown in. The power control device 71 includes an inverter 71a, an AND gate 71b, and an inverter 71c. The converter 71a inverts the value of the last cycle flag. The AND gate 71b calculates t...

Embodiment 3

[0148] The feature of Embodiment 3 is to change the instruction issuance restriction as a change in the processing state of the processor.

[0149] Figure 21 It is a structural block diagram of a processor related to Embodiment 3 of the present invention. Among the processors involved in Example 3, except image 3 The configuration of the processor according to the illustrated embodiment 1 further includes an instruction issuance control device 101.

[0150] The processing performed by the instruction decoding device 33 and the processing unit other than the instruction issuance control device 101 is the same as in the first embodiment. Accordingly, detailed description will not be repeated here.

[0151] The command decoding device 33 performs command issuance based on the control signal output from the command issuance control device 101.

[0152] The command issuance control device 101 controls the issuance of the command by the command decoding device 33 based on the information...

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PUM

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Abstract

A program execution control device which controls execution of a program by a processor having a predicate function for conditional execution of an instruction, wherein the program includes a branch instruction to control iterations in loop processing, the branch instruction is further an instruction to generate an execute-or-not condition indicating whether or not the branch instruction is to be executed at an iteration in the loop processing after a current iteration, and to reflect the execute-or-not condition on a predicate flag used for conditional execution of the branch instruction, the program execution control device comprises a processor status changing unit configured to change, before an execution cycle of the branch instruction, a status of the processor in advance for execution of an instruction following the branch instruction, the status being changed based on the execute-or-not condition reflected on the predicate flag.

Description

Technical field [0001] The invention relates to a program execution control device, which controls a program executed by a single or multiple microprocessors. Background technique [0002] In recent years, digital devices such as digital televisions, video recorders, and mobile phones need to perform digital processing such as sound processing, audio processing, moving image processing, and encoding processing, and graphical user interface (GUI: Graphical User Interface) operation processing. In addition, various demands such as making this digital device compatible with JAVA (registered trademark) are increasing. In order to achieve these requirements, information processing devices such as microprocessors (including microcomputers, microcontrollers, and digital signal processors (DSP)) are generally used. For these information processing devices, in accordance with the increase in the demand for application programs, in order to increase the processing capacity, the operating ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/32
CPCG06F9/325G06F9/3844G06F9/30072
Inventor 谷丈畅
Owner PANASONIC CORP