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Semiconductor device and method of manufacturing the same

A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as inability to achieve driving performance

Inactive Publication Date: 2009-03-04
SEIKO INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Accordingly, the trench width v, trench spacing 1, and trench depth w are limited, thereby providing a structure that cannot achieve further improvement in driving performance per unit area

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

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Comparison scheme
Effect test

no. 1 example

[0028] Figure 1 to Figure 4 A semiconductor device according to a first embodiment of the present invention is shown. figure 1 A lateral trench MOS transistor structure according to a first embodiment of the present invention is shown. figure 2 show includes figure 1 A cross-sectional view of the plane of the dashed-dotted line A-A' and the dashed-dotted line B-B'.

[0029] Such as figure 1 As shown, the n-type drain diffusion layer 201 and the n-type source diffusion layer 202 which become heavily doped impurity layers are formed on the p-type semiconductor substrate 101, and the gate insulating film 301 is formed on the p-type semiconductor substrate The substrate 101 is formed, and the gate electrode 401 is further formed on the gate insulating film 301 . In other words, the p-type semiconductor substrate 101, the n-type drain diffusion layer 201, the n-type source diffusion layer 202, and the gate electrode 401 serve as the substrate, drain, source, and gate of the...

no. 2 example

[0040] Figures 5 to 8 A semiconductor device according to a second embodiment of the present invention is shown. Figure 5 A lateral MOS transistor structure according to a second embodiment of the present invention is shown. Image 6 show includes Figure 5 Cross-sectional views of the planes of the dashed-dotted line D-D' and the dashed-dotted line E-E'.

[0041] Such as Figure 5 As shown, the n-type drain diffusion layer 201 and the n-type source diffusion layer 202 which become heavily doped impurity layers are formed on the p-type semiconductor substrate 101, and the gate insulating film 301 is formed on the p-type semiconductor substrate The substrate 101 is formed, and the gate electrode 401 is further formed on the gate insulating film 301 . The p-type semiconductor substrate 101, the n-type drain diffusion layer 201, the n-type source diffusion layer 202 and the gate electrode 401 are respectively used as the substrate, drain, source and gate of the MOS transist...

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Abstract

In a MOS transistor, a structure of trenches or fins arranged in parallel to a gate length direction is formed in a stepwise manner along a gate width direction to thereby reduce a step height of each step. Even if the MOS transistor includes a deep trench or a high fin in order to increase driving performance per unit area, a uniform impurity concentration in a channel region, a source diffusion layer, and a drain diffusion layer can be made by an ion implantation method. Accordingly, there can be obtained a stable characteristic that variation in the characteristic due to a surface on which the channel is formed does not appear, and a lateral MOS transistor with high driving performance having a reduced on-resistance per unit area can be provided.

Description

technical field [0001] The present invention relates to a semiconductor device including a metal oxide semiconductor (MOS) transistor having high driving performance. Background technique [0002] In applications requiring higher efficiency and higher output current for integrated circuits (ICs) such as voltage regulators (hereinafter denoted as VR) or switching regulators (hereinafter denoted as SWR) for controlling power supply voltage to output a constant voltage MOS transistors with low on-resistance are required. In this case, using an external power MOS transistor can satisfy the need for a MOS transistor with high drive performance. However, the number of components increases with the entire power control circuit, and therefore, there is a concern that the cost may increase due to the increase in the number of components and parts thereof. [0003] Incorporating external power MOS transistors into a VR or SWR can be a way to reduce costs. This combination allows si...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/10H01L29/08H01L29/06
CPCH01L29/78H01L29/1037H01L21/18
Inventor 北岛裕一郎
Owner SEIKO INSTR INC
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