Semiconductor package and manufacturing method thereof

A packaging and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of easy delamination of terminals and packaging colloids, poor bonding force of packaging colloids, etc., to reduce Delamination problem, avoid process inconvenience, avoid the effect of cost increase

Active Publication Date: 2009-05-13
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Furthermore, since the conductive circuit is only 5-10 microns thick and has poor bonding force with the encapsulant, delamination is likely to occur between the exposed terminal of the conductive circuit and the encapsulant

Method used

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  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0077] see Figure 2A FIG. 2H is a schematic cross-sectional view of the first embodiment of the semiconductor package and its manufacturing method of the present invention.

[0078] Such as Figure 2A As shown, first, a metal carrier (Carrier) 20 such as a copper plate (Cu Plate) is prepared, and a first resistance layer 21 is laid on one surface of the metal carrier 20, and the first resistance layer 21 is, for example, a photoresist layer (photo-resist), etc., and through exposure and development, the first resist layer 21 is formed with a through opening 210 that exposes a portion of the metal carrier 20 .

[0079] Then, a conductive metal layer 22 is formed in the first resistive layer opening 210, wherein the conductive metal layer 22 includes a die pad 221 corresponding to the position of the chip and an electrical connection terminal ( terminal) 222. The material of the conductive metal layer 22 is, for example, gold / nickel / copper (Au / Ni / Cu), nickel / gold (Ni / Au), go...

no. 2 example

[0092] Please refer to FIG. 3A to FIG. 3C , which are cross-sectional views of a second embodiment of the semiconductor package and its manufacturing method of the present invention. The semiconductor package and its manufacturing method of this embodiment are substantially the same as those of the foregoing embodiments, the main difference is that before forming the conductive metal layer, a plating layer of the same material as the metal carrier can be formed in the opening of the first resistance layer, so as to facilitate removal. When the metal carrier is used, the plating layer is removed at the same time, so that the conductive metal layer is recessed in the dielectric layer for connecting conductive elements.

[0093] As shown in FIG. 3A , a first resistive layer 31 is laid on a metal carrier 30 (for example, a copper plate), and a plurality of through openings 310 are opened at predetermined positions of the first resistive layer 31 to expose the metal carrier. 30 , t...

no. 3 example

[0097] Please refer to FIG. 4A and FIG. 4B , which are cross-sectional views of a third embodiment of the semiconductor package and its manufacturing method of the present invention.

[0098] The semiconductor package and its manufacturing method of this embodiment are substantially the same as those of the previous embodiments, the main difference is that the material of the conductive metal layer 42 is selected to be the same as that of the metal carrier 40, so that when the metal carrier 40 is removed by etching, Simultaneously etch part of the conductive metal layer 42, and control the etching amount of the conductive metal layer 42 (the depth of etching is about 10 microns), so that the conductive metal layer 42 is recessed in the dielectric layer 43, so that the conductive element 480 is effective fixed on the conductive metal layer 42 .

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PUM

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Abstract

The invention relates to a semiconductor packaging element and a preparation method thereof. A first resistance layer is paved on a metal carrier, and a plurality of through openings are arranged in the first resistance layer so that conductive metal layers can be formed in the openings; then the first resistance layer is removed, a dielectric layer is covered on one side of the metal carrier, which is provided with the conductive metal layers, and the dielectric layer is provided with dead holes to expose part of the conductive metal layers; then a conductive circuit is formed on the dielectric layer and a conductive poles are formed in the dead holes so that the conductive circuit is electrically connected to the conductive metal layers through the conductive poles, thereby the conductive circuit and the conductive metal layers utilizes the conductive poles to be effectively jointed with the dielectric layer so as to avoid the problem of layer escape; moreover, the dead holes formed in the dielectric layer are small so that the problems of inconvenient production process and cost increase which are resulted from large openings in the prior art can be avoided; then at least one chip is electrically connected to the conductive circuit and a wrapping chip, a packaging rubber body of the conductive circuit are formed, the metal carrier is removed, and then the semiconductor packaging element without a chip bearing component is formed.

Description

technical field [0001] The invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package without chip carrier and its manufacturing method. Background technique [0002] Traditional semiconductor chips use a lead frame as a chip carrier to form a semiconductor package. The lead frame includes a chip seat and a plurality of leads formed around the chip seat. After the semiconductor chip is bonded to the chip seat and the chip and the leads are electrically connected by welding wires, the lead frame is covered with an encapsulation resin. The chip, the chip seat, the bonding wire and the inner section of the lead form the semiconductor package with a lead frame. [0003] There are many types and types of semiconductor packages that use lead frames as chip carriers. As far as Quad Flat Non-leaded (QFN) semiconductor packages are concerned, they are characterized in that no external leads are provided, that is, There is no ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/60H01L21/56H01L23/488H01L23/31
CPCH01L2224/48091H01L2224/48227H01L2924/00014
Inventor 李春源黄建屏赖裕庭萧承旭柯俊吉
Owner SILICONWARE PRECISION IND CO LTD
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