Virtual functional units for VLIW processors

A technology of functional unit and processing unit, applied in the fields of electrical digital data processing, instruments, machine execution devices, etc., can solve the problems of high cost, inability to obtain additional area, complex multi-port LS units, etc.

Inactive Publication Date: 2009-10-07
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] Each LS unit is complex and expensive, so duplicating a second LS unit for the cluster is prohibitively expensive
A multi-ported LS unit that can sustain two load or sto

Method used

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  • Virtual functional units for VLIW processors
  • Virtual functional units for VLIW processors
  • Virtual functional units for VLIW processors

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Embodiment Construction

[0032] While the invention is susceptible to various modifications and alternative forms, details of the invention have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0033]Very long instruction word (VLIW) processors have functional processing units that operate in parallel for each instruction. VLIW instructions operate through individual issue slots (eg, eight issue slots). For each origination slot, multiple functional units can be used. Here, for the sake of simplicity, one functional unit per initiation slot is described. The NXP TriMedia architecture is an example of a design with multiple functional units per origination slot. The coun...

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Abstract

A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor. ''Virtual'' views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views. By providing multiple virtual views in multiple issue slots of a physical function unit, the compiler/scheduler has more freedom to schedule operations for the functional unit.

Description

technical field [0001] The present invention relates to microcomputer systems, and more particularly to VLIW processors having many initiator slots with bypass networks, and wherein a single physical function process is virtualized for two or more issue slots with bypass networks device unit. Background technique [0002] Processor design has advanced significantly over the past 50 years. Increasing semiconductor circuit density in general allows higher performance levels to be achieved using fewer components and at reduced cost. When implemented using CMOS process technology, low power implementations become possible. [0003] The embedded consumer market for audio and video processing is cost driven. Such devices were initially implemented using dedicated hardware that could provide the required performance at a lower price than was possible with programmable processors. Subsequently, the increased complexity of newer audio and video standards made programmability more...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3891G06F9/3824G06F9/3885G06F9/3828G06F9/3853
Inventor 让-威廉·范德韦尔特
Owner NXP BV
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