Delay unit, annular oscillator and PLL circuit

Abstract

The invention relates to a delay unit and an annular oscillator used for a semiconductor device, comprising a first delay branch and a second delay branch. The first delay branch is provided with a cophase input terminal used for receiving a differential signal and a cophase output terminal used for outputting the differential signal; the second delay branch is provided with an antiphase input terminal used for receiving the differential signal and an antiphase output terminal used for outputting the differential signal; the first delay branch and the second delay branch at least comprise an inverter and a transistor electrically connected with the inverter respectively; and the transistor receives a control signal, and the control signal is used for controlling the transistor to change the working voltage of the inverter connected with the transistor. The load resistance of the delay unit is changed with the control voltage so as to change the overturning delay of a delay unit circuit and form a symmetric structure of the delay unit simultaneously, thus guaranteeing the phase noise performance of the semiconductor devices or related circuits.

Description

technical field [0001] The invention relates to electronic devices and circuits, in particular to delay units, ring oscillators and PLL circuits of semiconductor devices. Background technique [0002] In the fields of electronics and communication, a Phase Locking Loop (PLL) uses an externally input reference signal to control the frequency and / or phase of an internal oscillation signal in the loop, and has been widely used. The core module of the PLL includes a voltage-controlled oscillator (Voltage Controlled Oscillator, VCO). The VCO structure and design directly affect the performance of the entire phase-locked loop. In today's highly integrated electronic products, low power consumption has become a necessary design index for electronic products, and the power consumption of PLL mainly comes from VCO. [0003] Because the oscillation frequency of the ring voltage-controlled oscillator is determined by the flipping delay td of each stage. The delay td of the primary d...

AI Technical Summary

Problems solved by technology

[0006] The inventors found that in the implementation of the present invention, in the delay unit of the prior art, a MOS tube (Metal-Oxide-Semiconductor Field-Effect-Transistor, Metal-Oxide-Semiconductor Field-Effect-Transistor) is generally used to form a variable capacitor. Change the gate voltage of the MOS tube to change the capacitance, and since the capacitance of the MOS tube does not change linearly with the gate voltage, the linear performance of this control method is not very good

At the same time, because the capacitance of the MOS capacitor is more sensitive to the gate voltage, this makes the phase detector gain Kvco of the VCO larger, which makes it difficult to guarantee the stability of the PLL system

In addition, since the VCO load current is constant, the power consumption of the VCO at any output frequency is constant, and since its load current is actually determined by the maximum output frequency, when the output frequency is low, the performance power consumption of the prior art than very low

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