High-speed bidirectional clock tree circuit applied to ultrahigh-speed analog-to-digital converter

Abstract

The invention provides a high-speed bidirectional clock tree circuit applied to an ultrahigh-speed analog-to-digital converter based on a CMOS process. An input end of the clock tree circuit is an double-end input, an output of a single-end output duty-factor input adjusting circuit (1) is connected with input ends of multi-path middle-stage buffer branches (2) at the same time, then an output end of each middle-stage buffer branch (2) is connected with the input ends of the multi-path middle-stage buffer branches (2) at the same time till the requirement of the required branch number is met, an output end of the last middle-stage buffer branch (2) is connected with an input end of a last tail-stage buffer branch (3), and the tail-stage buffer branch (3) finally outputs two paths of difference clocks. The circuit is deployed manually, and has a simple and symmetrical structure. By adopting common input of clock and control level, the circuit realizes the final output of the high-speed bidirectional clock with good duty factor by adjusting the input control level in the premise of different process deviation, and realizes a process fluctuation resisting bidirectional clock tree.

Description

technical field [0001] The invention relates to an integrated circuit for an ultra-high-speed analog-to-digital converter, which belongs to the technical field of integrated circuit design and manufacture. Background technique [0002] In the field of integrated circuits, clock trees are widely used in high-speed circuits. However, in the actual manufacturing process of chips, errors caused by process fluctuations are unavoidable. Especially in high-speed clock tree applications, if the error accumulates to a certain extent, it will cause problems such as inconsistent delay and duty cycle mismatch, which will cause the clock to work abnormally or even fail to work at all. [0003] In most high-speed circuit applications, bidirectional differential clocks are required, which imposes more precise requirements on the duty cycle of the output clock. [0004] Therefore, it becomes a problem that must be solved to realize a bidirectional clock that can realize a precise duty cyc...

AI Technical Summary

Problems solved by technology

However, in the actual manufacturing process of chips, errors caused by process fluctuations are unavoidable

Especially in high-speed clock tree applications, if the error accumulates to a certain extent, it will cause problems such as inconsistent delay and duty cycle mismatch, which will cause the clock to work abnormally or even fail to work at all.

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