Cover layer of semiconductor device interconnected structure and manufacturing method thereof

Abstract

The invention relates to a manufacturing method for a cover layer of a semiconductor device interconnected structure. The manufacturing method comprises the following steps: providing a semiconductor device interconnected structure matrix provided with interlevel dielectrics; forming a bottom cover layer on the interlevel dielectrics; forming a first sandwich layer in the bottom cover layer; and forming a top cover layer on the bottom cover layer and the first sandwich layer. Correspondingly, the invention also provides the cover layer of the semiconductor device interconnected structure. The invention adopts a compound medium layer as the cover layer of the semiconductor device interconnected structure, improves the mechanical strength of the whole interconnected structure and ensures that a chip is not easy to break in the use process. While further improving the mechanical strength of the whole interconnected structure, the metal material with higher thermal conduction in the cover layer can easily and timely dissipate heat generated in the working process of the chip so as to ensure that the chip cannot be burned down due to overhigh temperature and ensure the working efficiency and the stability of the chip.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a cover layer of a semiconductor device interconnection structure and a manufacturing method thereof. Background technique [0002] One of the challenges encountered in the field of integrated circuit design and manufacturing today is how to reduce the RC delay (Resistive Capacitive delay) of signal transmission. In this regard, one of the methods that the current technology has adopted is to replace aluminum interconnects with copper interconnects. Reduce the series resistance of metal interconnection lines; Another method is to reduce the parasitic capacitance between metal interconnection lines, which can be achieved by constructing porous (Porous) low dielectric constant (Low dielectric constant) in the dielectric layer between metal interconnection lines. k) material or air gap (Air Gap) to achieve. [0003] In addition, when the integrated circuit is wo...

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Problems solved by technology

[0006] In the existing method for making the interconnection structure of semiconductor devices, a single dielectric layer is generally used to form on the substrate of the interconnection structure of semiconductor devices, to seal the porous interlayer dielectric in the interlayer dielectric, or to seal the porous interlayer dielectric in the interlayer dielectric. The air gap is opened to form an air gap in the interlayer dielectric, which can reduce the parasitic capacitance between the metal wires of the semiconductor device interconnection structure to reduce the RC delay of signal transmission, but at the same time due to the porous structure or air in the interlayer dielectric The gap will also reduce the mechanical strength of the entire interconnection structure, making the chip easy to break during use, the electrical connection between the metal wires of the interconnection structure will be lost, and the circuit will not work normally; and the porous structure in the interlayer medium or The air gap usually also reduces the thermal conductivity of the entire interconnection structure, so that the heat generated by the circuit in the chip cannot be dissipated quickly, which may cause the inside of the chip to burn out due to excessive temperature, and then affect the entire circuit. Chip efficiency and stability

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