Sigma-Delta analog-to-digital converter

[0037] Embodiment 1. The block diagram of the Sigma-Delta analog-to-digital converter of the present invention is as attached Figure 5 As shown, it includes the prior art anti-aliasing filter 50, the sample-and-hold 51, the digital decimation filter 53, and the innovative analog modulator 52 of the present invention. The sample holder 51 is used for oversampling the analog input signal to reduce the quantization noise in the signal bandwidth, and the analog modulator 52 is used for noise shaping in the analog-to-digital conversion process. Oversampling and noise shaping are two key technologies of Sigma-Delta ADC. The analog modulator 52 uses a new type C inverter with application number 2009103013271 (patent name: Class C inverter using a body potential modulator) (the same below) instead of the traditional operational amplifier or the prior art class C inverter The new type C inverter is based on the prior art C type inverter 40, adding micro-power PMOS bulk modulator 41 and NMOS bulk modulator 42 (see application number 2009103013271 in PMOS bulk potential modulator and NMOS bulk potential modulator, the same below). Compared with the traditional operational amplifier, the new type C inverter greatly reduces the power consumption of the circuit. Compared with the prior art type C inverter, the new type C inverter overcomes the influence of process deviation on itself. Ensure the robustness and practicality of the analog-to-digital converter.

[0038] The prior art anti-aliasing filter 50 is used for anti-aliasing filtering of analog input signals. Since the sampling frequency f S Generally the signal band frequency f B The transmission band of the anti-aliasing filter is much larger than the pass bandwidth, and the first-order RC low-pass filter is sufficient to meet the loose anti-aliasing requirements.

[0039] Prior art sample holder 51, sampling frequency f S Higher, used for over sampling of analog input signal. In the Sigma-Delta analog-to-digital converter, there is usually no need for a special sample holder, and the input part of the modulator includes the signal sampling process.

[0040] The prior art digital decimation filter 53 includes a digital low-pass filter 57 and a decimation module 58. The digital low-pass filter 57 reduces the input signal bandwidth f B Other noises are filtered out, and then the sampling frequency f S Down to Nyquist frequency 2f B , And finally output the high-precision digital signal of Nyquist frequency.

[0041] The analog modulator 52 of the present invention is used for noise shaping in the analog-to-digital conversion process. It includes a loop filter 55, a feedforward ADC56a, a feedback DAC56b, an adder 54, and so on. The feedforward ADC56a and the feedback DAC56b are collectively called the coarse quantizer 56. The analog signal passes through the loop filter 55 and the feedforward ADC 56a in sequence after being oversampled by the sample-and-hold device, and outputs a high-speed and low-precision digital signal through coarse quantization. The digital signal is converted into an analog signal by the DAC56b in the feedback loop, and then the difference between the analog signal output by the DAC56b and the input signal is calculated by the adder 54 (mainly the quantization error E Q ), and feed it back to the loop filter 55 for accumulation. To eliminate these errors, the feedforward ADC 56a re-quantizes the error signal in the loop filter 55 and feeds it back to the modulator input. Taking one-bit quantization as an example, when the output of the loop filter 55 is positive, the reference signal fed back by the coarse quantizer 56 reduces the input signal of the loop filter. Similarly, when the output of the loop filter 55 is negative, the reference signal fed back by the coarse quantizer 56 increases the input signal. The feedback formed by the loop filter 55 and the coarse quantizer 56 finally makes the local average value of the quantized output track the local average value of the input signal, so as to realize accurate analog-to-digital conversion.

[0042] The loop filter 55 of the present invention is the main functional module and power consumption module of the analog modulator and even the entire analog-to-digital converter based on the new type C inverter. It contains one or more pseudo-differential structure switched capacitor integrators. The integrators form different transfer functions H(z) through the prior art single-loop series connection or multi-path cascade connection to realize loop filtering. The combination of the loop filter 55 and the coarse quantizer 56 can realize first-order or higher-order noise shaping and accurate analog-to-digital conversion. According to the composition of the integrator in the loop filter 55, the Sigma-Delta analog-to-digital converter (or analog modulator) can be divided into a high-order single-loop structure and a cascade structure. The high-order single-loop structure analog-to-digital converter will be described in detail in the second embodiment. The structure block diagram of the loop filter can be referred to Figure 7 The loop filter in 55, the specific circuit can refer to Figure 8 In the loop filter circuit 85.

[0043] The circuit structure diagram of the pseudo-differential structure switched capacitor integrator based on the new type C inverter is shown in the attached file. Image 6 , It includes two new type C inverters 60, two common-mode feedback circuits 61 of the prior art, a capacitor (sampling capacitor C S , Compensation capacitor C C And integrating capacitor C I ) And switch. Two of the new type C inverters 60 are respectively located in the positive and negative branches of the integrator. The two inverters are differentially symmetrical and form a pseudo-differential structure. They replace the operational amplifier or the operational amplifier in the prior art switched capacitor integrator. The location of the C-type inverter. The two common mode feedback circuits 61 respectively form common mode feedback in the positive and negative branches of the integrator. The power supply voltage of the new type C inverter is slightly lower than the sum of the threshold voltages of the two input tubes in the inverter. In the integrator, the new type C inverter can achieve high gain according to the bias voltage of the input terminal of different working phases. Two different working states of low power consumption and high slew rate and high current are as follows:

[0044] The switched capacitor integrator is divided into sampling phase and integration phase in actual work, and is controlled by two-phase non-overlapping clocks of p1 and p2.

[0045] The p1 phase is the sampling phase of the integrator, and the input signal IN is sampled to the capacitor C S Above, the offset voltage V of the new type C inverter 60 OFF Is sampled to the compensation capacitor C C , While integrating capacitance C I The charge stored in the previous phase is transferred to the next circuit. At this time, the input terminal node potential of the inverter is only the offset voltage of the inverter, which is close to the common mode level. The two input tubes M1 and M2 work in the weak inversion area, so the new type C inverter 60 has been In a stable state of high gain and low power consumption, while meeting the integrator's sampling phase requirements, it greatly reduces system power consumption.

[0046] The p2 phase is the integrated phase of the integrator, and the integrated phase includes a slewing phase and a settling phase. At the initial moment of the p2 phase, the integrator enters the establishment phase, and the sampling capacitor C S The potential of the bottom plate changes to the input common mode level V CM , Because the potential difference between the two ends of the capacitor will not change suddenly, so the sampling capacitor C S Both the upper plate and the inverter input node potential have a sudden change, and the inverter input node potential is pulled to -IN+V OFF. According to the polarity of the input signal, one of the input tubes in the inverter enters the strong inversion region from the previous weak inversion area, generating a considerable transient current, while the other one will be turned off immediately. New type C inverter 60 enters the state of high slew rate and high current, which just satisfies the higher requirement of the integrator for the current output capability of the inverter during phase establishment. Like the traditional integrator, the larger output current of the inverter causes the sampling capacitor C S The charge quickly transfers to the integrating capacitor C I transmission. Because of the integral capacitance C I The negative feedback effect of the inverter, the potential of the input node of the inverter is gradually restored to V OFF , And the compensation capacitor C C Always maintain V after p1 sampling phase OFF Therefore, the bottom plate of the compensation capacitor is compensated as a “virtual ground”. This autozeroing technology is used to improve the establishment accuracy of the integrator. Finally, the new type C inverter 60 re-enters high gain and low gain. In the steady state of power consumption, the integrator achieves stable establishment, and at this time the integrator enters the hold phase in the p2 phase. Since the inverter has an input tube in the cut-off region when establishing the phase inverter, and while maintaining the phase, both input tubes work in the weak inversion region, the entire integrator obtains a larger slew rate at the cost of the lowest static power consumption. ability.

[0047] For the new type C inverter, the prior art type C inverter 40 is used to implement the operational amplification function, and the micro-power PMOS bulk potential modulator 41 and the NMOS bulk potential modulator 42 are used to implement the inverter. The body potential of the PMOS input tube M1 and the NMOS input tube M2 of the inverter is modulated to reduce the process deviation. The steady-state characteristics (gain, bandwidth and static power consumption, etc.) and dynamic characteristics (slew rate, settling time, etc.) of the new type C inverter And dynamic power consumption, etc.).

[0048] For a switched capacitor integrator with a pseudo-differential structure, the key indicators such as operating frequency, settling time, integration accuracy and power consumption of the integrator are directly related to the new type C inverter. The present invention uses the body potential modulation effect of the body potential modulators 41 and 42 in the new type C inverter to make the various indicators of the pseudo-differential structure switched capacitor integrator relatively stable under different process angles without significantly increasing the power consumption.

[0049] For the entire analog-to-digital converter, the analog modulator 52 is the design focus and difficulty, and the loop filter 55 is the main functional module and power consumption module in the analog modulator 52, and the performance of the switched capacitor integrator directly affects To the effectiveness and accuracy of loop filtering in the modulator. Therefore, the introduction of a new type C inverter greatly improves the stability and robustness of the loop filter 55 and even the entire analog-to-digital converter.

[0050] In practical applications, in order to achieve high-precision analog-to-digital conversion, the Sigma-Delta analog-to-digital converter (or analog modulator 52) generally adopts a high-order single-loop structure or a cascade structure.

[0051] Embodiment 2: The third-order single-ring structure Sigma-Delta analog-to-digital converter proposed by the present invention is characterized in that the analog modulator therein is a third-order single-ring structure. Attached Figure 7 It is a structural block diagram of a third-order single-loop analog modulator, which includes three pseudo-differential structure switched capacitor integrators 70, 71 and 72 and two adders 54, 73 and coarse quantizer 56 of the prior art. Among them, three integrators 70, 71, and 72 are connected in series in a single loop to form a loop filter 55. The coarse quantizer 56 includes a feedforward ADC56a and a feedback DAC56b. It can be used in combination with the loop filter 55 to achieve a third-order Noise shaping and precise analog-to-digital conversion. c1, c2, and c3 are the scaling factors of the modulator, which are used to scale the signal so that within the input range of the modulator, the output swing of the integrator does not exceed its linear output range. In the third-order single-loop structure Sigma-Delta analog-to-digital converter, the loop filter 55 (ie integrators 70, 71 and 72) is the main power consumption module, so the pseudo-differential structure based on the new type C inverter is adopted The switched capacitor integrator can greatly reduce the system power consumption while ensuring robustness and practicability.

[0052] The third-order single-loop structure Sigma-Delta analog-to-digital converter of the present invention adopts the feedforward structure of the prior art, that is, three feedforward paths and an adder 73 are newly added to the analog modulator. The three feedforward paths respectively start from the analog signal input terminal and the output terminals of the switched capacitor integrators 70 and 71 of the previous two-stage pseudo-differential structure, and are finally combined at the input terminal of the coarse quantizer 56 through the adder 73. Among them, a1, a2, a3, and a4 are the coefficients on the feedforward branch of the modulator, which are used to optimize the noise shaping. After calculation, the coefficients on the feeder branch meet the following conditions: a1=1, a2c1=3, a3c1c2=3, a4c1c2c3=1, the output Y and the input X have the following relationship:

[0053] Y=X+(1-z -1 ) 3 E Q

[0054] E in the above formula Q The quantization noise introduced for the quantizer. It can be seen from the above formula that the signal transfer function STF(z)=1 from the input X to the output Y of the analog modulator of the feedforward structure, that is, the integrator only needs to deal with the quantization noise and does not deal with the analog input signal, which can reduce The sensitivity of the modulator to the non-ideality of the new type C inverter in the integrator. Therefore, this structure can realize a highly linear analog modulator and a Sigma-Delta analog-to-digital converter without increasing the power consumption of the circuit.

[0055] It should be noted that the high-order single-loop Sigma-Delta analog-to-digital converter does not have very high requirements for the gain of the new type C inverter. System-level simulation shows that when the oversampling rate is 128, the inverter gain is about 30dB to ensure that the dynamic range loss caused by insufficient gain is less than 1dB. Through circuit-level simulation, it can be seen that under SMIC (Semiconductor International) 0.13um process, the power supply voltage is 1.2V, the aspect ratio of M1 and M3 is 180μm/0.35μm, and the aspect ratio of M2 and M4 is 60μm/0.35μm. When the aspect ratio of M5 and M6 is 1/8 of M1 and M2, and the load capacitance of the inverter is 5pF, the gain of the new type C inverter reaches about 48dB. Therefore, the gain of the new type C inverter fully meets the demand, and can directly replace the traditional operational amplifier in the high-order single-loop Sigma-Delta analog-to-digital converter to achieve the purpose of reducing power consumption.

[0056] The circuit diagram of the third-order single-loop analog modulator is as attached Figure 8 As shown, it is implemented using a fully differential switched capacitor circuit, including three pseudo-differential structure switched capacitor integrator circuits 80, 81 and 82, a comparator circuit 83 (one-bit quantization), a feedback DAC circuit 84, and an adder, etc. Part, where the switches include PMOS switches NMOS switch CMOS switch And bootstrap NMOS switch And other types, the capacitor includes the sampling capacitor C S , Compensation capacitor C C 、Integrating capacitance C I , Common mode feedback capacitor C M And feedforward capacitor C F Integrator circuits 80, 81, and 82 are connected in series to form a loop filter circuit 85 in a single loop. Attached Figure 8 Sub-paths and sub-circuits and attached Figure 7 There is a one-to-one correspondence, and the entire circuit includes:

[0057] Two feedback paths, starting from the positive and negative output terminals D and Db of the comparator circuit 83, respectively output FB+ and FB- to the signal input terminals IN+ and IN- through the feedback DAC circuit 84;

[0058] Six feedforward paths, two of which start from the analog signal input terminals IN+ and IN-, and pass through the feedforward capacitor C F1 To the input terminal of the comparator circuit 83; the two feedforward paths respectively start from the output terminals OUT1+ and OUT1- of the first-stage integrator circuit 80 through the feedforward capacitor C F2 To the input terminal of the comparator circuit 83; the other two start from the output terminals OUT2+ and OUT2- of the second-stage integrator circuit 81, and pass through the feedforward capacitor C F3 To the input terminal of the comparator circuit 83.

[0059] Two adder circuits, two feedback paths are combined with the signal input terminals IN+ and IN- respectively, and pass through the sampling capacitor C in the first-stage integrator circuit 80 s1 The adder 54 is realized, and the six feed-forward paths are respectively combined at the positive and negative input terminals of the coarse quantizer (that is, the positive and negative output terminals OUT3+ and OUT3- of the third-stage integrator circuit 82), and pass the feedforward capacitor C F1 , C F2 , C F3 And C F4 Implement the adder 73.

[0060] The three pseudo-differential structure switched capacitor integrator circuits 80, 81 and 82, and the operational amplifiers in the three integrators are all replaced with two differentially symmetrical new type C inverters. Normally, the operational amplifier in the integrator is the most important power consumption part of the analog modulator. Therefore, the use of a switched capacitor integrator with a pseudo-differential structure based on a novel inverter in the present invention can greatly reduce the power consumption of the system while ensuring the performance of the analog-to-digital converter, and improve the stability and robustness of the circuit.

[0061] A comparator circuit 83, for the sake of simplicity, a comparator circuit 83 is used in the cascade modulator to realize one-bit quantization, and the comparator circuit 83 can be regarded as the quantizer 56 with the simplest structure.

[0062] The two feedback DAC circuits 84 are implemented by a switch network. For example, when the modulator output is high, the feedback signal FB=VREF+; on the contrary, if the modulator outputs a low level, the feedback signal FB=VREF-. For the 1.2V power supply voltage, VREF+=1V and VREF-=0.2V are generally selected. Therefore, the switch connected to VREF+ adopts a PMOS switch, and the switch connected to VREF- adopts an NMOS switch to realize reliable conduction of the feedback reference voltage.

[0063] Capacitance C between the input of the modulator B1 And C B2 The interference introduced by the package pins and bonding wires to a certain differential input terminal is coupled to another input terminal, so that this interference signal becomes the common mode input of the modulator, and then it is suppressed by a fully differential circuit.

[0064] The timing diagram of the clock phase in the third-order single-loop analog modulator is attached Picture 9 As shown, p1 is the sampling phase, p2 is the integration phase, and the falling edges of p1a and p2a are slightly ahead of p1 and p2 to suppress channel charge injection related to the input signal. The control clock p1ab of the comparator lags behind p1 and leads p2 to avoid the influence of signal delay on the comparison accuracy.

[0065] For the first-stage integrator circuit 80, at the p1 phase, the input signal IN and the feedback signal FB are sampled to the sampling capacitor C through the bootstrap NMOS switch and the CMOS switch, respectively S1 On; in the p2 phase, the charge corresponding to the voltage difference between the input signal IN and the feedback signal FB1 is transferred from C through the CMOS switch S1 Transfer to C I1. Among them, the modulator scaling factor c1 is determined by the ratio of the sampling capacitor to the integrating capacitor C S1 /C I1 Decided.

[0066] For the second and third-stage integrator circuits 81, 82, due to the effects of second-order and third-order noise shaping respectively, the requirements for signal sampling linearity are reduced, so the signals OUT1 and OUT2 are respectively sampled to C through CMOS switches S2 And C S3. Similarly, the modulator scaling factors c2 and c3 are respectively determined by C s2 /C I2 , C S3 /C I3 Decided.

[0067] The modulator coefficients a1, a2, a3 and a4 are determined by the feedforward capacitor C F1 , C F2 , C F3 And C F4 The ratio between the decision, by selecting the appropriate capacitor value can achieve the reasonable scaling of the signal and the best optimization of noise shaping.