Under bump metal layer, wafer level chip scale package structure and forming method thereof

Abstract

The invention provides a method for forming an under bump metal layer, which comprises the following steps: forming a metal substrate layer and a passivation layer for protecting the surface of a chipand exposing the metal substrate layer on the chip; after sequentially forming a first metal layer and a photoresist layer on the passivation layer and the metal substrate layer, and forming an opening on the photoresist layer, wherein the first metal layer on the metal substrate layer is exposed at the opening; in the opening, sequentially forming a second metal layer which comprises a solder layer on the first metal layer; and etching the first metal layer until the passivation layer is exposed after the photoresist layer is removed, and forming the under bump metal layer by the etched first metal layer and the second metal layer. The invention also provides the under bump metal layer, a wafer level chip scale package structure and a forming method thereof. The method for forming the under bump metal layer improves the electrical performance and the reliability of a film.

Description

technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to an under-bump metal layer, a wafer level chip scale package (Wafer Level chip Scale Package, WLCSP) structure and a forming method. Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the...

AI Technical Summary

Problems solved by technology

[0012] In the process of forming wafer-level chip size packaging in the prior art, the surface of the seed layer made of metal is easily oxidized, which reduces the electrical performance and reliability of the subsequently formed chip

Images