Under bump metal layer, wafer level chip scale package structure and forming method thereof

A metal layer under bump, wafer-level chip technology, which is applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc. Electrical properties and reliability, improved adhesion, good wetting effect

Inactive Publication Date: 2010-02-10
SEMICON MFG INT (SHANGHAI) CORP
View PDF1 Cites 14 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] In the process of forming wafer-level chip size packaging in the prior art, the surface of the seed layer made of metal is easily oxidized, which reduces the electrical performance and reliability of the subsequently formed chip

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Under bump metal layer, wafer level chip scale package structure and forming method thereof
  • Under bump metal layer, wafer level chip scale package structure and forming method thereof
  • Under bump metal layer, wafer level chip scale package structure and forming method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0034] Figure 6 It is a flowchart of a specific embodiment of forming an under-bump metal layer in the present invention. Executing step S201, forming a metal pad layer and a passivation layer for protecting the surface of the chip and exposing the metal pad layer on the chip; executing step S202, forming a first metal layer and a photolithography layer on the passivation layer and the metal pad layer After the adhesive layer, an opening is formed on the photoresist layer, and the opening exposes the first metal layer on the metal pad layer; step S203 is performed, and in the opening, a second metal layer is sequentially formed on the first metal layer, and the first metal layer is sequentially formed on the first metal layer. The second metal layer includes a solder layer and a conductive layer under the solder layer; perform step S204,...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to view more

Abstract

The invention provides a method for forming an under bump metal layer, which comprises the following steps: forming a metal substrate layer and a passivation layer for protecting the surface of a chipand exposing the metal substrate layer on the chip; after sequentially forming a first metal layer and a photoresist layer on the passivation layer and the metal substrate layer, and forming an opening on the photoresist layer, wherein the first metal layer on the metal substrate layer is exposed at the opening; in the opening, sequentially forming a second metal layer which comprises a solder layer on the first metal layer; and etching the first metal layer until the passivation layer is exposed after the photoresist layer is removed, and forming the under bump metal layer by the etched first metal layer and the second metal layer. The invention also provides the under bump metal layer, a wafer level chip scale package structure and a forming method thereof. The method for forming the under bump metal layer improves the electrical performance and the reliability of a film.

Description

technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to an under-bump metal layer, a wafer level chip scale package (Wafer Level chip Scale Package, WLCSP) structure and a forming method. Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/485
CPCH01L24/11H01L2224/11H01L2924/14H01L2924/00H01L2924/00012
Inventor 丁万春孟津
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap