Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices

Abstract

The invention discloses an interdigital structure capable of regulating the channel current of vertical gate SOI CMOS devices, which comprises a plurality of vertical gate SOI CMOS devices which are distributed in parallel, wherein PMOS regions of the adjacent vertical gate SOI CMOS devices are adjacent, and NMOS regions are also adjacent; source regions of all of the vertical gate SOI CMOS devices are positioned on the same side, and drain regions are positioned on the other side; and gate electrodes of all of the vertical gate SOI CMOS devices are led out of the side surface to form interdigital gate electrodes. The adjacent PMOS regions share one body electrode; the adjacent NMOS regions share one body electrode; and all of the body electrodes are connected in parallel to form an interdigital body electrode. All source electrodes led out from the source regions are connected in parallel to form an interdigital source electrode; and all drain electrodes led out from the drain regions are connected in parallel to form an interdigital drain electrode. In the invention, the gate electrodes of the plurality of the CMOS devices are connected in parallel by an interdigital topological structure, which is equivalent to improving the equivalent gate width of the vertical gate SOI CMOS devices so as to fulfill the aim of regulating the channel current of the vertical gate SOI CMOS devices.

Description

Technical field [0001] The invention belongs to the technical field of microelectronics and solid electronics, and relates to an interdigital structure capable of adjusting the channel current of a vertical gate SOI CMOS device. Background technique [0002] Silicon On Insulator (SOI) refers to the substrate technology that replaces the traditional bulk silicon substrate with an "engineered" substrate. This substrate usually consists of the following three layers: a thin single crystal silicon top layer on top An etching circuit is formed; a relatively thin buried oxide (BOX) layer, that is, an insulating silicon dioxide intermediate layer; a very thick bulk substrate silicon substrate layer, whose main function is to provide mechanical support for the upper two layers. Since the oxide layer in the SOI structure separates the silicon film layer on it from the silicon substrate layer, the large-area p-n junction will be replaced by dielectric isolation. The source region and drai...

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Problems solved by technology

[0005] However, the channel length of the vertical gate SOI CMOS device structure can be extended by changing the layout, but the channel width is limited by the thickness of the top silicon, so there is a bottleneck in the design, that is, the maximum channel width is smaller than the top silicon of the SOI substrate. In this way, it is impossible to design a vertical gate SOI CMOS device with a relatively large channel width. For discrete or multiple SOI CMOS devices of the same type, the design purpose can be achieved by selecting a specific top silicon thickness, but if A variety of CMOS devices with different channel widths are involved in the circuit, the channel width must be easy to adjust, so as to achieve the purpose of adjusting the channel current of the vertical gate SOI CMOS device

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